ee5585ed09
Improve and enable folding of conditional branches with tail calls. 1. Make it so that conditional tail calls can be emitted even when there are multiple predecessors. 2. Don't guard the transformation behind -Os. The rationale for guarding it was static-prediction can be affected by whether the branch is forward of backward. This is no longer true for almost any X86 cpus (anything newer than `SnB`) so is no longer a meaningful concern. Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D140931
102 lines
3.1 KiB
LLVM
102 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
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; PR31455 - https://bugs.llvm.org/show_bug.cgi?id=31455
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; We have to assume that errno can be set, so we have to make a libcall in that case.
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; But it's better for perf to check that the argument is valid rather than the result of
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; sqrtss/sqrtsd.
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; Note: This is really a test of the -partially-inline-libcalls IR pass (and we have an IR test
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; for that), but we're checking the final asm to make sure that comes out as expected too.
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define float @f(float %val) nounwind {
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; SSE-LABEL: f:
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; SSE: # %bb.0:
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; SSE-NEXT: xorps %xmm1, %xmm1
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; SSE-NEXT: ucomiss %xmm1, %xmm0
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; SSE-NEXT: jb sqrtf # TAILCALL
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; SSE-NEXT: # %bb.1: # %.split
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; SSE-NEXT: sqrtss %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: f:
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; AVX: # %bb.0:
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; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vucomiss %xmm1, %xmm0
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; AVX-NEXT: jb sqrtf # TAILCALL
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; AVX-NEXT: # %bb.1: # %.split
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; AVX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%res = tail call float @sqrtf(float %val)
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ret float %res
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}
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define double @d(double %val) nounwind {
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; SSE-LABEL: d:
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; SSE: # %bb.0:
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; SSE-NEXT: xorpd %xmm1, %xmm1
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; SSE-NEXT: ucomisd %xmm1, %xmm0
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; SSE-NEXT: jb sqrt # TAILCALL
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; SSE-NEXT: # %bb.1: # %.split
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; SSE-NEXT: sqrtsd %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: d:
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; AVX: # %bb.0:
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; AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vucomisd %xmm1, %xmm0
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; AVX-NEXT: jb sqrt # TAILCALL
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; AVX-NEXT: # %bb.1: # %.split
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; AVX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%res = tail call double @sqrt(double %val)
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ret double %res
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}
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define double @minsize(double %x, double %y) minsize {
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; SSE-LABEL: minsize:
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; SSE: # %bb.0:
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; SSE-NEXT: mulsd %xmm0, %xmm0
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; SSE-NEXT: mulsd %xmm1, %xmm1
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; SSE-NEXT: addsd %xmm0, %xmm1
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; SSE-NEXT: sqrtsd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: minsize:
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; AVX: # %bb.0:
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; AVX-NEXT: vmulsd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vmulsd %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vaddsd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%t3 = fmul fast double %x, %x
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%t4 = fmul fast double %y, %y
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%t5 = fadd fast double %t3, %t4
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%t6 = tail call fast double @llvm.sqrt.f64(double %t5)
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ret double %t6
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}
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; Partial reg avoidance may involve register allocation
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; rather than adding an instruction.
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define double @partial_dep_minsize(double %x, double %y) minsize {
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; SSE-LABEL: partial_dep_minsize:
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; SSE: # %bb.0:
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; SSE-NEXT: sqrtsd %xmm1, %xmm0
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; SSE-NEXT: addsd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: partial_dep_minsize:
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; AVX: # %bb.0:
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; AVX-NEXT: vsqrtsd %xmm1, %xmm1, %xmm0
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; AVX-NEXT: vaddsd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%t6 = tail call fast double @llvm.sqrt.f64(double %y)
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%t = fadd fast double %t6, %y
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ret double %t
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}
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declare dso_local float @sqrtf(float)
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declare dso_local double @sqrt(double)
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declare dso_local double @llvm.sqrt.f64(double)
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