c9017bc793
1. Map R16-R31 to DWARF registers 130-145. 2. Make R16-R31 caller-saved registers. 3. Make R16-31 allocatable only when feature EGPR is supported 4. Make R16-31 availabe for instructions in legacy maps 0/1 and EVEX space, except XSAVE*/XRSTOR RFC: https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4 Explanations for some seemingly unrelated changes: inline-asm-registers.mir, statepoint-invoke-ra-enter-at-end.mir: The immediate (TargetInstrInfo.cpp:1612) used for the regdef/reguse is the encoding for the register class in the enum generated by tablegen. This encoding will change any time a new register class is added. Since the number is part of the input, this means it can become stale. seh-directive-errors.s: R16-R31 makes ".seh_pushreg 17" legal musttail-varargs.ll: It seems some LLVM passes use the number of registers rather the number of allocatable registers as heuristic. This PR is to reland #67702 after #70222 in order to reduce some compile-time regression when EGPR is not used.
119 lines
3.4 KiB
ArmAsm
119 lines
3.4 KiB
ArmAsm
# RUN: not llvm-mc -triple x86_64-windows-msvc %s -filetype=obj -o /dev/null 2>&1 | FileCheck %s --implicit-check-not=error:
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# RUN: not llvm-mc -triple x86_64-windows-msvc %s -o /dev/null 2>&1 | FileCheck %s --implicit-check-not=error:
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.text
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# CHECK: error: .seh_ directive must appear within an active frame
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.seh_handlerdata
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.seh_pushreg %rsi
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# CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: .seh_ directive must appear within an active frame
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.seh_stackalloc 32
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# CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: .seh_ directive must appear within an active frame
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.def f;
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.scl 2;
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.type 32;
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.endef
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.globl f # -- Begin function f
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.p2align 4, 0x90
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f: # @f
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.seh_proc f
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pushq %rsi
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.seh_pushreg %rsi
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pushq %rdi
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.seh_pushreg %rdi
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pushq %rbx
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.seh_pushreg %rbx
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subq $32, %rsp
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.seh_stackalloc 0
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# CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: stack allocation size must be non-zero
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.seh_stackalloc 7
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# CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: stack allocation size is not a multiple of 8
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.seh_stackalloc 32
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.seh_endprologue
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nop
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addq $32, %rsp
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popq %rbx
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popq %rdi
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popq %rsi
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retq
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.seh_handlerdata
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.text
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.seh_endproc
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.seh_pushreg %rsi
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# CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: .seh_ directive must appear within an active frame
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g:
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.seh_proc g
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pushq %rbp
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.seh_pushreg %rbx
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pushq %rsi
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.seh_pushreg %rsi
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.seh_endprologue
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.seh_setframe 3 255
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# CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: you must specify a stack pointer offset
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.seh_setframe 3, 255
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# CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: offset is not a multiple of 16
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.seh_setframe 3, 256
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# CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: frame offset must be less than or equal to 240
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.seh_setframe 3, 128
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.seh_setframe 3, 128
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# CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: frame register and offset can be set at most once
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nop
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popq %rsi
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popq %rbp
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retq
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.seh_endproc
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.globl h # -- Begin function h
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.p2align 4, 0x90
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h: # @h
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.seh_proc h
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# %bb.0: # %entry
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subq $72, %rsp
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.seh_stackalloc 72
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movaps %xmm7, 48(%rsp) # 16-byte Spill
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.seh_savexmm 7 44
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# CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: you must specify an offset on the stack
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.seh_savexmm %xmm7, 44
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# CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: offset is not a multiple of 16
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.seh_savexmm %xmm7, 48
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movaps %xmm6, 32(%rsp) # 16-byte Spill
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.seh_savexmm %xmm6, 32
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.seh_endprologue
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movapd %xmm0, %xmm6
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callq getdbl
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movapd %xmm0, %xmm7
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addsd %xmm6, %xmm7
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callq getdbl
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addsd %xmm7, %xmm0
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movaps 32(%rsp), %xmm6 # 16-byte Reload
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movaps 48(%rsp), %xmm7 # 16-byte Reload
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addq $72, %rsp
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retq
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.seh_handlerdata
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.text
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.seh_endproc
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# -- End function
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.globl i
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.def i; .scl 2; .type 32; .endef
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.p2align 4, 0x90
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i:
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.seh_proc i
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pushq %rbp
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.seh_pushreg 32
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# CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: incorrect register number for use with this directive
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pushq %rbx
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.seh_pushreg %xmm0
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# CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: register is not supported for use with this directive
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leaq 16(%rsp), %rbp
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.seh_setframe %xmm0, 16
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# CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: register is not supported for use with this directive
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.seh_endprologue
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ret
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.seh_endproc
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