8e8c954a17
This tries to fix a bug by resolving a few FIXMEs. The bug is that
`EraseInstAction` is emitted after emitting the _first_ `BuildMIAction`,
which is too early because the erased instruction may still be used by
subsequent `BuildMIAction`s (in particular, by `CopyRenderer`).
An example of the bug (from `match-table-operand-types.td`):
```
def InstTest0 : GICombineRule<
(defs root:$a),
(match (G_MUL i32:$x, i32:$b, i32:$c),
(G_MUL $a, i32:$b, i32:$x)),
(apply (G_ADD i64:$tmp, $b, i32:$c),
(G_ADD i8:$a, $b, i64:$tmp))>;
GIR_EraseFromParent, /*InsnID*/0,
GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_ADD),
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // a
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // b
GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0,
```
Here, the root instruction is destroyed before copying its operands ('a'
and 'b') to the new instruction.
The solution is to emit `EraseInstAction` for the root instruction as
the last action in the emission pipeline.
86 lines
4.3 KiB
TableGen
86 lines
4.3 KiB
TableGen
// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
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include "llvm/Target/Target.td"
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def TestTargetInstrInfo : InstrInfo;
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def TestTarget : Target {
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let InstructionSet = TestTargetInstrInfo;
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}
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def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
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def SPECIAL : Register<"special"> { let Namespace = "MyTarget"; }
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def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
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def Special32 : RegisterClass<"MyTarget", [i32], 32, (add SPECIAL)>;
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class I<dag OOps, dag IOps, list<dag> Pat>
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: Instruction {
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let Namespace = "MyTarget";
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let OutOperandList = OOps;
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let InOperandList = IOps;
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let Pattern = Pat;
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}
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// Try a normal physical register use.
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// GISEL: GIM_Try,
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// GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
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// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD),
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// GISEL-NEXT: // MIs[0] DstI[dst]
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// GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
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// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
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// GISEL-NEXT: // MIs[0] src0
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// GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
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// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
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// GISEL-NEXT: // MIs[0] Operand 2
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// GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
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// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::Special32RegClassID),
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// GISEL-NEXT: // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src0, SPECIAL:{ *:[i32] }) => (ADD_PHYS:{ *:[i32] } GPR32:{ *:[i32] }:$src0)
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// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
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// GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
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// GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // SPECIAL
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// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ADD_PHYS),
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// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
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// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
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// GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
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// GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0,
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def ADD_PHYS : I<(outs GPR32:$dst), (ins GPR32:$src0),
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[(set GPR32:$dst, (add GPR32:$src0, SPECIAL))]> {
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let Uses = [SPECIAL];
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}
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// Try using the name of the physreg in another operand.
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// GISEL: GIM_Try,
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// GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
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// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL),
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// GISEL-NEXT: // MIs[0] DstI[dst]
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// GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
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// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
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// GISEL-NEXT: // MIs[0] SPECIAL
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// GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
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// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
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// GISEL-NEXT: // MIs[0] Operand 2
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// GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
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// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::Special32RegClassID),
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// GISEL-NEXT: // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$SPECIAL, SPECIAL:{ *:[i32] }) => (MUL_PHYS:{ *:[i32] } GPR32:{ *:[i32] }:$SPECIAL)
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// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
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// GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
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// GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // SPECIAL
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// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MUL_PHYS),
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// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
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// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // SPECIAL
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// GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
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// GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0,
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def MUL_PHYS : I<(outs GPR32:$dst), (ins GPR32:$SPECIAL),
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[(set GPR32:$dst, (mul GPR32:$SPECIAL, SPECIAL))]> {
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let Uses = [SPECIAL];
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}
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// Try giving the physical operand a name
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// def ADD_PHYS : I<(outs GPR32:$dst), (ins GPR32:$src0),
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// [(set GPR32:$dst, (add GPR32:$src0, SPECIAL:$special))]> {
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// let Uses = [SPECIAL];
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// }
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