a60deaa204
The pass uses the TTI hook getIntImmCostIntrin that only supports scalar integer types. Whilst hoisting expensive vector constant is likely worthwhile, this is new behaviour and so I've followed the path taken by the GEP variant of collectConstantCandidates and simply bail for vector types.
160 lines
5.9 KiB
LLVM
160 lines
5.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
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; RUN: opt -mtriple=arm64-darwin-unknown -S -passes=consthoist < %s | FileCheck %s --check-prefixes=CHECK,CV
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; RUN: opt -mtriple=arm64-darwin-unknown -S -passes=consthoist -use-constant-int-for-fixed-length-splat -use-constant-int-for-scalable-splat < %s | FileCheck %s --check-prefixes=CHECK,CI
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define i128 @test1(i128 %a) {
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; CHECK-LABEL: define i128 @test1(
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; CHECK-SAME: i128 [[A:%.*]]) {
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; CHECK-NEXT: [[CONST:%.*]] = bitcast i128 12297829382473034410122878 to i128
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; CHECK-NEXT: [[TMP1:%.*]] = add i128 [[A]], [[CONST]]
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; CHECK-NEXT: [[TMP2:%.*]] = add i128 [[TMP1]], [[CONST]]
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; CHECK-NEXT: ret i128 [[TMP2]]
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;
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%1 = add i128 %a, 12297829382473034410122878
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%2 = add i128 %1, 12297829382473034410122878
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ret i128 %2
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}
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; Check that we don't hoist large, but cheap constants
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define i512 @test2(i512 %a) {
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; CHECK-LABEL: define i512 @test2(
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; CHECK-SAME: i512 [[A:%.*]]) {
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; CHECK-NEXT: [[TMP1:%.*]] = and i512 [[A]], 7
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; CHECK-NEXT: [[TMP2:%.*]] = or i512 [[TMP1]], 7
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; CHECK-NEXT: ret i512 [[TMP2]]
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;
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%1 = and i512 %a, 7
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%2 = or i512 %1, 7
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ret i512 %2
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}
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; Check that we don't hoist the shift value of a shift instruction.
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define i512 @test3(i512 %a) {
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; CHECK-LABEL: define i512 @test3(
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; CHECK-SAME: i512 [[A:%.*]]) {
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; CHECK-NEXT: [[TMP1:%.*]] = shl i512 [[A]], 504
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; CHECK-NEXT: [[TMP2:%.*]] = ashr i512 [[TMP1]], 504
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; CHECK-NEXT: ret i512 [[TMP2]]
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;
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%1 = shl i512 %a, 504
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%2 = ashr i512 %1, 504
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ret i512 %2
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}
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; Ensure the code generator has the information necessary to simply sdiv.
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define i64 @sdiv(i64 %a) {
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; CHECK-LABEL: define i64 @sdiv(
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; CHECK-SAME: i64 [[A:%.*]]) {
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; CHECK-NEXT: [[TMP1:%.*]] = sdiv i64 [[A]], 4294967087
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; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 4294967087
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; CHECK-NEXT: ret i64 [[TMP2]]
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;
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%1 = sdiv i64 %a, 4294967087
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%2 = add i64 %1, 4294967087
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ret i64 %2
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}
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; Ensure the code generator has the information necessary to simply srem.
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define i64 @srem(i64 %a) {
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; CHECK-LABEL: define i64 @srem(
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; CHECK-SAME: i64 [[A:%.*]]) {
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; CHECK-NEXT: [[TMP1:%.*]] = srem i64 [[A]], 4294967087
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; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 4294967087
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; CHECK-NEXT: ret i64 [[TMP2]]
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;
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%1 = srem i64 %a, 4294967087
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%2 = add i64 %1, 4294967087
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ret i64 %2
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}
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; Ensure the code generator has the information necessary to simply udiv.
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define i64 @udiv(i64 %a) {
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; CHECK-LABEL: define i64 @udiv(
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; CHECK-SAME: i64 [[A:%.*]]) {
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; CHECK-NEXT: [[TMP1:%.*]] = udiv i64 [[A]], 4294967087
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; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 4294967087
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; CHECK-NEXT: ret i64 [[TMP2]]
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;
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%1 = udiv i64 %a, 4294967087
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%2 = add i64 %1, 4294967087
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ret i64 %2
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}
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; Ensure the code generator has the information necessary to simply urem.
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define i64 @urem(i64 %a) {
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; CHECK-LABEL: define i64 @urem(
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; CHECK-SAME: i64 [[A:%.*]]) {
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; CHECK-NEXT: [[TMP1:%.*]] = urem i64 [[A]], 4294967087
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; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 4294967087
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; CHECK-NEXT: ret i64 [[TMP2]]
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;
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%1 = urem i64 %a, 4294967087
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%2 = add i64 %1, 4294967087
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ret i64 %2
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}
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; Code generator will not decompose divide like operations when the divisor is
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; no a constant.
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define i64 @sdiv_non_const_divisor(i64 %a) {
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; CHECK-LABEL: define i64 @sdiv_non_const_divisor(
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; CHECK-SAME: i64 [[A:%.*]]) {
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; CHECK-NEXT: [[CONST:%.*]] = bitcast i64 4294967087 to i64
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; CHECK-NEXT: [[TMP1:%.*]] = sdiv i64 [[CONST]], [[A]]
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; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], [[CONST]]
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; CHECK-NEXT: ret i64 [[TMP2]]
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;
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%1 = sdiv i64 4294967087, %a
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%2 = add i64 %1, 4294967087
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ret i64 %2
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}
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; Code generator emits divide instructions when optimising for size.
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define i64 @sdiv_minsize(i64 %a) minsize {
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; CHECK-LABEL: define i64 @sdiv_minsize(
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; CHECK-SAME: i64 [[A:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[CONST:%.*]] = bitcast i64 4294967087 to i64
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; CHECK-NEXT: [[TMP1:%.*]] = sdiv i64 [[A]], [[CONST]]
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; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], [[CONST]]
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; CHECK-NEXT: ret i64 [[TMP2]]
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;
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%1 = sdiv i64 %a, 4294967087
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%2 = add i64 %1, 4294967087
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ret i64 %2
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}
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define <2 x i64> @sdiv_v2i64(<2 x i64> %a) {
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; CV-LABEL: define <2 x i64> @sdiv_v2i64(
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; CV-SAME: <2 x i64> [[A:%.*]]) {
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; CV-NEXT: [[TMP1:%.*]] = sdiv <2 x i64> [[A]], <i64 4294967087, i64 4294967087>
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; CV-NEXT: [[TMP2:%.*]] = add <2 x i64> [[TMP1]], <i64 4294967087, i64 4294967087>
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; CV-NEXT: ret <2 x i64> [[TMP2]]
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;
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; CI-LABEL: define <2 x i64> @sdiv_v2i64(
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; CI-SAME: <2 x i64> [[A:%.*]]) {
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; CI-NEXT: [[TMP1:%.*]] = sdiv <2 x i64> [[A]], splat (i64 4294967087)
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; CI-NEXT: [[TMP2:%.*]] = add <2 x i64> [[TMP1]], splat (i64 4294967087)
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; CI-NEXT: ret <2 x i64> [[TMP2]]
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;
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%1 = sdiv <2 x i64> %a, <i64 4294967087, i64 4294967087>
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%2 = add <2 x i64> %1, <i64 4294967087, i64 4294967087>
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ret <2 x i64> %2
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}
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define <vscale x 2 x i64> @sdiv_nxv2i64(<vscale x 2 x i64> %a) {
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; CV-LABEL: define <vscale x 2 x i64> @sdiv_nxv2i64(
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; CV-SAME: <vscale x 2 x i64> [[A:%.*]]) {
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; CV-NEXT: [[TMP1:%.*]] = sdiv <vscale x 2 x i64> [[A]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 4294967087, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
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; CV-NEXT: [[TMP2:%.*]] = add <vscale x 2 x i64> [[TMP1]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 4294967087, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
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; CV-NEXT: ret <vscale x 2 x i64> [[TMP2]]
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;
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; CI-LABEL: define <vscale x 2 x i64> @sdiv_nxv2i64(
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; CI-SAME: <vscale x 2 x i64> [[A:%.*]]) {
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; CI-NEXT: [[TMP1:%.*]] = sdiv <vscale x 2 x i64> [[A]], splat (i64 4294967087)
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; CI-NEXT: [[TMP2:%.*]] = add <vscale x 2 x i64> [[TMP1]], splat (i64 4294967087)
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; CI-NEXT: ret <vscale x 2 x i64> [[TMP2]]
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;
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%1 = sdiv <vscale x 2 x i64> %a, splat (i64 4294967087)
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%2 = add <vscale x 2 x i64> %1, splat (i64 4294967087)
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ret <vscale x 2 x i64> %2
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}
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