eecb99c5f6
These tests rely on SCEV looking recognizing an "or" with no common bits as an "add". Add the disjoint flag to relevant or instructions in preparation for switching SCEV to use the flag instead of the ValueTracking query. The IR with disjoint flag matches what InstCombine would produce.
204 lines
7.0 KiB
LLVM
204 lines
7.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=indvars -replexitval=always -S | FileCheck %s
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; Make sure IndVars preserves LCSSA form, especially across loop nests.
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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define void @PR18642(i32 %x) {
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; CHECK-LABEL: @PR18642(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[OUTER_HEADER:%.*]]
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; CHECK: outer.header:
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; CHECK-NEXT: br label [[INNER_HEADER:%.*]]
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; CHECK: inner.header:
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; CHECK-NEXT: br i1 false, label [[INNER_LATCH:%.*]], label [[OUTER_LATCH:%.*]]
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; CHECK: inner.latch:
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; CHECK-NEXT: br i1 true, label [[INNER_HEADER]], label [[EXIT_LOOPEXIT:%.*]]
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; CHECK: outer.latch:
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; CHECK-NEXT: br i1 false, label [[OUTER_HEADER]], label [[EXIT_LOOPEXIT1:%.*]]
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; CHECK: exit.loopexit:
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; CHECK-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ -2147483648, [[INNER_LATCH]] ]
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; CHECK-NEXT: br label [[EXIT:%.*]]
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; CHECK: exit.loopexit1:
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; CHECK-NEXT: br label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: [[EXIT_PHI:%.*]] = phi i32 [ [[INC_LCSSA]], [[EXIT_LOOPEXIT]] ], [ undef, [[EXIT_LOOPEXIT1]] ]
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; CHECK-NEXT: ret void
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;
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entry:
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br label %outer.header
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outer.header:
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%outer.iv = phi i32 [ 0, %entry ], [ %x, %outer.latch ]
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br label %inner.header
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inner.header:
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%inner.iv = phi i32 [ undef, %outer.header ], [ %inc, %inner.latch ]
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%cmp1 = icmp slt i32 %inner.iv, %outer.iv
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br i1 %cmp1, label %inner.latch, label %outer.latch
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inner.latch:
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%inc = add nsw i32 %inner.iv, 1
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%cmp2 = icmp slt i32 %inner.iv, %outer.iv
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br i1 %cmp2, label %inner.header, label %exit
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outer.latch:
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br i1 undef, label %outer.header, label %exit
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exit:
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%exit.phi = phi i32 [ %inc, %inner.latch ], [ undef, %outer.latch ]
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ret void
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}
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define i64 @unconditional_exit_simplification(i64 %arg) {
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; CHECK-LABEL: @unconditional_exit_simplification(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP1:%.*]]
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; CHECK: loop1:
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; CHECK-NEXT: br label [[LOOP2:%.*]]
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; CHECK: loop2:
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; CHECK-NEXT: [[IV2:%.*]] = phi i64 [ 0, [[LOOP1]] ], [ 1, [[LOOP2]] ]
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; CHECK-NEXT: br i1 true, label [[LOOP2]], label [[LOOP1_LATCH:%.*]]
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; CHECK: loop1.latch:
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; CHECK-NEXT: [[RES_LCSSA:%.*]] = phi i64 [ [[IV2]], [[LOOP2]] ]
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; CHECK-NEXT: br i1 false, label [[LOOP1]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[RES_LCSSA2:%.*]] = phi i64 [ [[RES_LCSSA]], [[LOOP1_LATCH]] ]
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; CHECK-NEXT: ret i64 [[RES_LCSSA2]]
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;
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entry:
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br label %loop1
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loop1:
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%iv1 = phi i64 [ 0, %entry ], [ 1, %loop1.latch ]
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br label %loop2
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loop2:
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%iv2 = phi i64 [ 0, %loop1 ], [ 1, %loop2 ]
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%res = add nuw nsw i64 %iv1, %iv2
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br i1 true, label %loop2, label %loop1.latch
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loop1.latch:
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%res.lcssa = phi i64 [ %res, %loop2 ]
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br i1 false, label %loop1, label %exit
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exit:
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%res.lcssa2 = phi i64 [ %res.lcssa, %loop1.latch ]
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ret i64 %res.lcssa2
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}
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; Check that it does not crash because the incoming values of an LCSSA phi are
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; equal.
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define void @pr57000(i64 %a) {
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; CHECK-LABEL: @pr57000(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP_1_OUTER:%.*]]
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; CHECK: loop.1.loopexit:
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; CHECK-NEXT: br label [[LOOP_1_OUTER]]
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; CHECK: loop.1.outer:
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; CHECK-NEXT: br label [[LOOP_1:%.*]]
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; CHECK: loop.1:
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; CHECK-NEXT: [[CMP:%.*]] = icmp sle i64 [[A:%.*]], 2546175499358690212
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; CHECK-NEXT: [[CMP_EXT:%.*]] = zext i1 [[CMP]] to i8
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; CHECK-NEXT: br i1 [[CMP]], label [[LOOP_1]], label [[LOOP_2_HEADER_PREHEADER:%.*]]
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; CHECK: loop.2.header.preheader:
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; CHECK-NEXT: [[CMP_LCSSA2:%.*]] = phi i1 [ [[CMP]], [[LOOP_1]] ]
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; CHECK-NEXT: [[CMP_EXT_LCSSA:%.*]] = phi i8 [ [[CMP_EXT]], [[LOOP_1]] ]
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; CHECK-NEXT: br label [[LOOP_2_HEADER_OUTER:%.*]]
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; CHECK: loop.2.header.outer:
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; CHECK-NEXT: br label [[LOOP_2_HEADER:%.*]]
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; CHECK: loop.2.header:
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; CHECK-NEXT: switch i8 [[CMP_EXT_LCSSA]], label [[LOOP_1_LOOPEXIT:%.*]] [
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; CHECK-NEXT: i8 -1, label [[LOOP_2_LATCH:%.*]]
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; CHECK-NEXT: i8 1, label [[LOOP_2_LATCH]]
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; CHECK-NEXT: i8 4, label [[LOOP_2_HEADER]]
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; CHECK-NEXT: ]
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; CHECK: loop.2.latch:
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; CHECK-NEXT: [[CMP_TRUNC_LCSSA1:%.*]] = phi i1 [ [[CMP_LCSSA2]], [[LOOP_2_HEADER]] ], [ [[CMP_LCSSA2]], [[LOOP_2_HEADER]] ]
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; CHECK-NEXT: call void @use(i1 [[CMP_TRUNC_LCSSA1]])
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; CHECK-NEXT: br label [[LOOP_2_HEADER_OUTER]]
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;
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entry:
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br label %loop.1
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loop.1:
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%p.1 = phi i1 [ 0 , %entry ], [ %p.1, %loop.1 ], [ %p.2, %loop.2.header ]
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%cmp = icmp sle i64 %a, 2546175499358690212
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%cmp.ext = zext i1 %cmp to i8
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br i1 %cmp, label %loop.1, label %loop.2.header
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loop.2.header:
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%p.2 = phi i1 [ %p.1, %loop.1 ], [ %p.2, %loop.2.header ], [ %cmp, %loop.2.latch ]
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%cmp.trunc = trunc i8 %cmp.ext to i1
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switch i8 %cmp.ext, label %loop.1 [
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i8 -1, label %loop.2.latch
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i8 1, label %loop.2.latch
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i8 4, label %loop.2.header
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]
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loop.2.latch:
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call void @use(i1 %cmp.trunc)
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br label %loop.2.header
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}
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define void @D149435(i16 %arg) {
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; CHECK-LABEL: @D149435(
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; CHECK-NEXT: br label [[LOOP1:%.*]]
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; CHECK: loop1:
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; CHECK-NEXT: [[FR:%.*]] = freeze i16 [[ARG:%.*]]
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; CHECK-NEXT: [[ARRAYIDX_IDX:%.*]] = shl i16 [[FR]], 1
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; CHECK-NEXT: [[OR:%.*]] = or disjoint i16 [[ARRAYIDX_IDX]], 1
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; CHECK-NEXT: br i1 false, label [[LOOP1]], label [[LOOP2_PREHEADER:%.*]]
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; CHECK: loop2.preheader:
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; CHECK-NEXT: [[FR_LCSSA:%.*]] = phi i16 [ [[FR]], [[LOOP1]] ]
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; CHECK-NEXT: [[OR_LCSSA:%.*]] = phi i16 [ [[OR]], [[LOOP1]] ]
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; CHECK-NEXT: [[UMAX:%.*]] = call i16 @llvm.umax.i16(i16 [[OR_LCSSA]], i16 2)
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; CHECK-NEXT: [[TMP1:%.*]] = add i16 [[UMAX]], -1
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; CHECK-NEXT: [[TMP2:%.*]] = shl i16 [[FR_LCSSA]], 1
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; CHECK-NEXT: [[TMP3:%.*]] = sub i16 [[TMP1]], [[TMP2]]
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; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i16 [[TMP3]], 0
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; CHECK-NEXT: [[UMAX1:%.*]] = call i16 @llvm.umax.i16(i16 [[ARG]], i16 2)
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; CHECK-NEXT: [[TMP5:%.*]] = sub i16 [[UMAX1]], [[ARG]]
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; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i16 [[TMP5]], 0
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; CHECK-NEXT: br label [[LOOP2:%.*]]
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; CHECK: loop2:
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; CHECK-NEXT: br i1 [[TMP4]], label [[TRAP:%.*]], label [[FOR_BODY8:%.*]]
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; CHECK: for.body8:
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; CHECK-NEXT: br i1 [[TMP6]], label [[TRAP]], label [[LOOP2_LATCH:%.*]]
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; CHECK: loop2.latch:
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; CHECK-NEXT: br i1 false, label [[LOOP2]], label [[TRAP]]
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; CHECK: trap:
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; CHECK-NEXT: unreachable
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;
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br label %loop1
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loop1:
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%fr = freeze i16 %arg
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%arrayidx.idx = shl i16 %fr, 1
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%or = or disjoint i16 %arrayidx.idx, 1
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br i1 false, label %loop1, label %loop2.preheader
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loop2.preheader:
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br label %loop2
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loop2:
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%iv = phi i16 [ %iv.next, %loop2.latch ], [ 0, %loop2.preheader ]
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%add = add i16 %or, %iv
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%cmp = icmp ugt i16 %add, 1
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br i1 %cmp, label %trap, label %for.body8
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for.body8:
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%add2 = add i16 %arg, %iv
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%cmp2 = icmp ugt i16 %add2, 1
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br i1 %cmp2, label %trap, label %loop2.latch
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loop2.latch:
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%iv.next = add i16 %iv, 1
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br i1 false, label %loop2, label %trap
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trap:
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unreachable
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}
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declare void @use(i1)
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