0676acb6fd
Should cover most of the tests for GVN, GVNHoist, GVNSink, GlobalOpt, GlobalSplit, InstCombine, Reassociate, SROA and TailCallElim that had not been updated earlier.
114 lines
3.2 KiB
LLVM
114 lines
3.2 KiB
LLVM
; RUN: opt -passes=instcombine -S < %s | FileCheck %s
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;
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; void func(long n, double A[static const restrict n]) {
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; for (int i = 0; i < n; i+=1)
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; for (int j = 0; j < n;j+=1)
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; for (int k = 0; k < n; k += 1)
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; for (int l = 0; l < n; l += 1) {
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; ptr p = &A[i + j + k + l];
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; double x = *p;
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; double y = *p;
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; arg(x + y);
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; }
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; }
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;
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; Check for correctly merging access group metadata for instcombine
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; (only common loops are parallel == intersection)
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; Note that combined load would be parallel to loop !16 since both
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; origin loads are parallel to it, but it references two access groups
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; (!8 and !9), neither of which contain both loads. As such, the
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; information that the combined load is parallel to !16 is lost.
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;
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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declare void @arg(double)
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define void @func(i64 %n, ptr noalias nonnull %A) {
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entry:
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br label %for.cond
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for.cond:
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%i.0 = phi i32 [ 0, %entry ], [ %add31, %for.inc30 ]
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%conv = sext i32 %i.0 to i64
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%cmp = icmp slt i64 %conv, %n
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br i1 %cmp, label %for.cond2, label %for.end32
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for.cond2:
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%j.0 = phi i32 [ %add28, %for.inc27 ], [ 0, %for.cond ]
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%conv3 = sext i32 %j.0 to i64
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%cmp4 = icmp slt i64 %conv3, %n
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br i1 %cmp4, label %for.cond8, label %for.inc30
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for.cond8:
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%k.0 = phi i32 [ %add25, %for.inc24 ], [ 0, %for.cond2 ]
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%conv9 = sext i32 %k.0 to i64
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%cmp10 = icmp slt i64 %conv9, %n
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br i1 %cmp10, label %for.cond14, label %for.inc27
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for.cond14:
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%l.0 = phi i32 [ %add23, %for.body19 ], [ 0, %for.cond8 ]
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%conv15 = sext i32 %l.0 to i64
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%cmp16 = icmp slt i64 %conv15, %n
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br i1 %cmp16, label %for.body19, label %for.inc24
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for.body19:
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%add = add nsw i32 %i.0, %j.0
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%add20 = add nsw i32 %add, %k.0
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%add21 = add nsw i32 %add20, %l.0
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%idxprom = sext i32 %add21 to i64
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%arrayidx = getelementptr inbounds double, ptr %A, i64 %idxprom
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%0 = load double, ptr %arrayidx, align 8, !llvm.access.group !1
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%1 = load double, ptr %arrayidx, align 8, !llvm.access.group !2
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%add22 = fadd double %0, %1
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call void @arg(double %add22), !llvm.access.group !3
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%add23 = add nsw i32 %l.0, 1
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br label %for.cond14, !llvm.loop !11
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for.inc24:
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%add25 = add nsw i32 %k.0, 1
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br label %for.cond8, !llvm.loop !14
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for.inc27:
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%add28 = add nsw i32 %j.0, 1
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br label %for.cond2, !llvm.loop !16
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for.inc30:
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%add31 = add nsw i32 %i.0, 1
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br label %for.cond, !llvm.loop !18
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for.end32:
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ret void
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}
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; access groups
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!7 = distinct !{}
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!8 = distinct !{}
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!9 = distinct !{}
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; access group lists
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!1 = !{!7, !9}
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!2 = !{!7, !8}
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!3 = !{!7, !8, !9}
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!11 = distinct !{!11, !13}
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!13 = !{!"llvm.loop.parallel_accesses", !7}
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!14 = distinct !{!14, !15}
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!15 = !{!"llvm.loop.parallel_accesses", !8}
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!16 = distinct !{!16, !17}
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!17 = !{!"llvm.loop.parallel_accesses", !8, !9}
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!18 = distinct !{!18, !19}
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!19 = !{!"llvm.loop.parallel_accesses", !9}
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; CHECK: load double, {{.*}} !llvm.access.group ![[ACCESSGROUP_0:[0-9]+]]
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; CHECK: br label %for.cond14, !llvm.loop ![[LOOP_4:[0-9]+]]
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; CHECK: ![[ACCESSGROUP_0]] = distinct !{}
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; CHECK: ![[LOOP_4]] = distinct !{![[LOOP_4]], ![[PARALLEL_ACCESSES_5:[0-9]+]]}
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; CHECK: ![[PARALLEL_ACCESSES_5]] = !{!"llvm.loop.parallel_accesses", ![[ACCESSGROUP_0]]}
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