cb8d83a77c
The assertion in #80597 failed when we were trying to compute known bits
of a value in an unreachable BB.
859b09da08/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp (L749-L810)
In this case, `SignBits` is 30 (deduced from instr info), but `Known` is
`10000101010111010011110101000?0?00000000000000000000000000000000`
(deduced from dom cond). Setting high bits of `lshr Known, 1` will lead
to conflict.
This patch masks out high bits of `Known.Zero` to address this problem.
Fixes #80597.
34 lines
1.1 KiB
LLVM
34 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt -S -passes=instcombine < %s | FileCheck %s
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define i64 @pr80597(i1 %cond) {
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; CHECK-LABEL: define i64 @pr80597(
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; CHECK-SAME: i1 [[COND:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[ADD:%.*]] = select i1 [[COND]], i64 0, i64 -12884901888
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; CHECK-NEXT: [[SEXT1:%.*]] = add nsw i64 [[ADD]], 8836839514384105472
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; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[SEXT1]], -34359738368
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; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
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; CHECK: if.else:
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; CHECK-NEXT: [[SEXT2:%.*]] = ashr exact i64 [[ADD]], 1
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; CHECK-NEXT: [[ASHR:%.*]] = or i64 [[SEXT2]], 4418419761487020032
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; CHECK-NEXT: ret i64 [[ASHR]]
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; CHECK: if.then:
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; CHECK-NEXT: ret i64 0
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;
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entry:
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%add = select i1 %cond, i64 0, i64 4294967293
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%add8 = shl i64 %add, 32
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%sext1 = add i64 %add8, 8836839514384105472
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%cmp = icmp ult i64 %sext1, -34359738368
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br i1 %cmp, label %if.then, label %if.else
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if.else:
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%sext2 = or i64 %add8, 8836839522974040064
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%ashr = ashr i64 %sext2, 1
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ret i64 %ashr
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if.then:
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ret i64 0
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}
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