fd07b8f809
This is mostly NFC but some output does change due to consistently inserting into poison rather than undef and using i64 as the index type for inserts.
191 lines
5.0 KiB
LLVM
191 lines
5.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=instcombine -S | FileCheck %s
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define i64 @test1(i32 %x) nounwind {
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: ret i64 0
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;
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%y = lshr i32 %x, 1
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%r = udiv i32 %y, -1
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%z = sext i32 %r to i64
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ret i64 %z
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}
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define i64 @test2(i32 %x) nounwind {
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: ret i64 0
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;
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%y = lshr i32 %x, 31
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%r = udiv i32 %y, 3
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%z = sext i32 %r to i64
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ret i64 %z
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}
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; The udiv instructions shouldn't be optimized away, and the
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; sext instructions should be optimized to zext.
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define i64 @test1_PR2274(i32 %x, i32 %g) nounwind {
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; CHECK-LABEL: @test1_PR2274(
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; CHECK-NEXT: [[Y:%.*]] = lshr i32 [[X:%.*]], 30
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; CHECK-NEXT: [[R:%.*]] = udiv i32 [[Y]], [[G:%.*]]
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; CHECK-NEXT: [[Z:%.*]] = zext nneg i32 [[R]] to i64
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; CHECK-NEXT: ret i64 [[Z]]
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;
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%y = lshr i32 %x, 30
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%r = udiv i32 %y, %g
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%z = sext i32 %r to i64
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ret i64 %z
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}
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define i64 @test2_PR2274(i32 %x, i32 %v) nounwind {
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; CHECK-LABEL: @test2_PR2274(
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; CHECK-NEXT: [[Y:%.*]] = lshr i32 [[X:%.*]], 31
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; CHECK-NEXT: [[R:%.*]] = udiv i32 [[Y]], [[V:%.*]]
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; CHECK-NEXT: [[Z:%.*]] = zext nneg i32 [[R]] to i64
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; CHECK-NEXT: ret i64 [[Z]]
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;
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%y = lshr i32 %x, 31
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%r = udiv i32 %y, %v
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%z = sext i32 %r to i64
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ret i64 %z
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}
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; The udiv should be simplified according to the rule:
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; X udiv (C1 << N), where C1 is `1<<C2` --> X >> (N+C2)
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@b = external global [1 x i16]
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define i32 @PR30366(i1 %a) {
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; CHECK-LABEL: @PR30366(
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; CHECK-NEXT: [[Z:%.*]] = zext i1 [[A:%.*]] to i32
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; CHECK-NEXT: [[Z2:%.*]] = zext nneg i16 shl (i16 1, i16 ptrtoint (ptr @b to i16)) to i32
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; CHECK-NEXT: [[D:%.*]] = udiv i32 [[Z]], [[Z2]]
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; CHECK-NEXT: ret i32 [[D]]
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;
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%z = zext i1 %a to i32
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%z2 = zext i16 shl (i16 1, i16 ptrtoint (ptr @b to i16)) to i32
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%d = udiv i32 %z, %z2
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ret i32 %d
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}
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; OSS-Fuzz #4857
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; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=4857
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define i177 @ossfuzz_4857(i177 %X, i177 %Y) {
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; CHECK-LABEL: @ossfuzz_4857(
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; CHECK-NEXT: store i1 poison, ptr undef, align 1
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; CHECK-NEXT: ret i177 0
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;
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%B5 = udiv i177 %Y, -1
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%B4 = add i177 %B5, -1
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%B2 = add i177 %B4, -1
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%B6 = mul i177 %B5, %B2
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%B3 = add i177 %B2, %B2
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%B9 = xor i177 %B4, %B3
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%B13 = ashr i177 %Y, %B2
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%B22 = add i177 %B9, %B13
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%B1 = udiv i177 %B5, %B6
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%C9 = icmp ult i177 %Y, %B22
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store i1 %C9, ptr undef
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ret i177 %B1
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}
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; 2 low bits are not needed because 12 has 2 trailing zeros
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define i8 @udiv_demanded_low_bits_set(i8 %a) {
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; CHECK-LABEL: @udiv_demanded_low_bits_set(
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; CHECK-NEXT: [[U:%.*]] = udiv i8 [[A:%.*]], 12
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; CHECK-NEXT: ret i8 [[U]]
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;
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%o = or i8 %a, 3
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%u = udiv i8 %o, 12
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ret i8 %u
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}
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; This can't divide evenly, so it is poison.
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define i8 @udiv_exact_demanded_low_bits_set(i8 %a) {
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; CHECK-LABEL: @udiv_exact_demanded_low_bits_set(
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; CHECK-NEXT: ret i8 poison
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;
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%o = or i8 %a, 3
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%u = udiv exact i8 %o, 12
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ret i8 %u
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}
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; All high bits are set, so this simplifies.
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define i8 @udiv_demanded_high_bits_set(i8 %x, i8 %y) {
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; CHECK-LABEL: @udiv_demanded_high_bits_set(
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; CHECK-NEXT: ret i8 21
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;
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%o = or i8 %x, -4
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%r = udiv i8 %o, 12
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ret i8 %r
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}
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; This should fold the same as above.
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define i8 @udiv_exact_demanded_high_bits_set(i8 %x, i8 %y) {
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; CHECK-LABEL: @udiv_exact_demanded_high_bits_set(
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; CHECK-NEXT: ret i8 21
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;
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%o = or i8 %x, -4
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%r = udiv exact i8 %o, 12
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ret i8 %r
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}
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; 2 low bits are not needed because 12 has 2 trailing zeros
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define i8 @udiv_demanded_low_bits_clear(i8 %a) {
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; CHECK-LABEL: @udiv_demanded_low_bits_clear(
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; CHECK-NEXT: [[U:%.*]] = udiv i8 [[A:%.*]], 12
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; CHECK-NEXT: ret i8 [[U]]
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;
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%o = and i8 %a, -4
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%u = udiv i8 %o, 12
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ret i8 %u
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}
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; This should fold the same as above.
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define i8 @udiv_exact_demanded_low_bits_clear(i8 %a) {
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; CHECK-LABEL: @udiv_exact_demanded_low_bits_clear(
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; CHECK-NEXT: [[U:%.*]] = udiv i8 [[A:%.*]], 12
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; CHECK-NEXT: ret i8 [[U]]
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;
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%o = and i8 %a, -4
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%u = udiv exact i8 %o, 12
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ret i8 %u
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}
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define <vscale x 1 x i32> @udiv_demanded3(<vscale x 1 x i32> %a) {
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; CHECK-LABEL: @udiv_demanded3(
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; CHECK-NEXT: [[U:%.*]] = udiv <vscale x 1 x i32> [[A:%.*]], shufflevector (<vscale x 1 x i32> insertelement (<vscale x 1 x i32> poison, i32 12, i64 0), <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer)
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; CHECK-NEXT: ret <vscale x 1 x i32> [[U]]
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;
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%o = or <vscale x 1 x i32> %a, splat (i32 3)
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%u = udiv <vscale x 1 x i32> %o, splat (i32 12)
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ret <vscale x 1 x i32> %u
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}
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; PR74242
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define i32 @div_by_zero_or_one_from_dom_cond(i32 %a, i32 %b) {
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; CHECK-LABEL: @div_by_zero_or_one_from_dom_cond(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[A:%.*]], 1
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; CHECK-NEXT: br i1 [[CMP]], label [[JOIN:%.*]], label [[ZERO_OR_ONE:%.*]]
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; CHECK: zero_or_one:
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; CHECK-NEXT: br label [[JOIN]]
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; CHECK: join:
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; CHECK-NEXT: ret i32 [[B:%.*]]
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;
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entry:
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%cmp = icmp ugt i32 %a, 1
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br i1 %cmp, label %join, label %zero_or_one
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zero_or_one:
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%div = udiv i32 %b, %a
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br label %join
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join:
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%res = phi i32 [ %div, %zero_or_one ], [ %b, %entry ]
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ret i32 %res
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}
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