e44a305690
https://alive2.llvm.org/ce/z/2iC4oB This is similar to changes made for zext + lshr:21d3871b7c6c39a3aae1The existing fold did not account for extra uses, so we see some instruction count reductions in the test diffs. This is intended to improve analysis (icmp likely has more transforms than any other opcode), make other transforms more symmetric with zext/lshr, and it can be inverted in codegen if profitable. As with the earlier changes, there is potential to uncover infinite combine loops, but I have not found any yet.
67 lines
2.7 KiB
LLVM
67 lines
2.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=instcombine -S | FileCheck %s
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define <4 x i32> @vec_select(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: @vec_select(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, [[A:%.*]]
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; CHECK-NEXT: [[ISNEG:%.*]] = icmp slt <4 x i32> [[B:%.*]], zeroinitializer
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; CHECK-NEXT: [[T2:%.*]] = select <4 x i1> [[ISNEG]], <4 x i32> zeroinitializer, <4 x i32> [[A]]
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; CHECK-NEXT: [[ISNEG1:%.*]] = icmp slt <4 x i32> [[B]], zeroinitializer
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; CHECK-NEXT: [[T3:%.*]] = select <4 x i1> [[ISNEG1]], <4 x i32> [[SUB]], <4 x i32> zeroinitializer
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; CHECK-NEXT: [[COND:%.*]] = or <4 x i32> [[T2]], [[T3]]
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; CHECK-NEXT: ret <4 x i32> [[COND]]
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;
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%cmp = icmp slt <4 x i32> %b, zeroinitializer
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%sub = sub nsw <4 x i32> zeroinitializer, %a
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%t0 = icmp slt <4 x i32> %sext, zeroinitializer
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%sext3 = sext <4 x i1> %t0 to <4 x i32>
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%t1 = xor <4 x i32> %sext3, <i32 -1, i32 -1, i32 -1, i32 -1>
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%t2 = and <4 x i32> %a, %t1
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%t3 = and <4 x i32> %sext3, %sub
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%cond = or <4 x i32> %t2, %t3
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ret <4 x i32> %cond
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}
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define <4 x i32> @vec_select_alternate_sign_bit_test(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: @vec_select_alternate_sign_bit_test(
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, [[A:%.*]]
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; CHECK-NEXT: [[CMP1:%.*]] = icmp slt <4 x i32> [[B:%.*]], zeroinitializer
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; CHECK-NEXT: [[COND:%.*]] = select <4 x i1> [[CMP1]], <4 x i32> [[A]], <4 x i32> [[SUB]]
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; CHECK-NEXT: ret <4 x i32> [[COND]]
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;
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%cmp = icmp sgt <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%sub = sub nsw <4 x i32> zeroinitializer, %a
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%t0 = icmp slt <4 x i32> %sext, zeroinitializer
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%sext3 = sext <4 x i1> %t0 to <4 x i32>
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%t1 = xor <4 x i32> %sext3, <i32 -1, i32 -1, i32 -1, i32 -1>
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%t2 = and <4 x i32> %a, %t1
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%t3 = and <4 x i32> %sext3, %sub
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%cond = or <4 x i32> %t2, %t3
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ret <4 x i32> %cond
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}
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define <2 x i32> @is_negative_undef_elt(<2 x i32> %a) {
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; CHECK-LABEL: @is_negative_undef_elt(
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; CHECK-NEXT: [[A_LOBIT:%.*]] = ashr <2 x i32> [[A:%.*]], <i32 31, i32 31>
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; CHECK-NEXT: ret <2 x i32> [[A_LOBIT]]
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;
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%cmp = icmp slt <2 x i32> %a, <i32 0, i32 undef>
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%sext = sext <2 x i1> %cmp to <2 x i32>
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ret <2 x i32> %sext
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}
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define <2 x i32> @is_positive_undef_elt(<2 x i32> %a) {
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; CHECK-LABEL: @is_positive_undef_elt(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[A:%.*]], <i32 undef, i32 -1>
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; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i1> [[CMP]] to <2 x i32>
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; CHECK-NEXT: ret <2 x i32> [[SEXT]]
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;
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%cmp = icmp sgt <2 x i32> %a, <i32 undef, i32 -1>
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%sext = sext <2 x i1> %cmp to <2 x i32>
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ret <2 x i32> %sext
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}
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