db158c7c83
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen. Differential Revision: https://reviews.llvm.org/D156799
173 lines
6.3 KiB
LLVM
173 lines
6.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
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target datalayout = "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128"
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; we need to generate post index load for this case
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define i32 @test(i32 %c, ptr %a, ptr %b) {
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; CHECK-LABEL: test:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w0, #1
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; CHECK-NEXT: b.lt .LBB0_4
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; CHECK-NEXT: // %bb.1: // %for.body.preheader
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; CHECK-NEXT: mov w8, w0
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; CHECK-NEXT: .LBB0_2: // %for.body
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldr w9, [x1], #4
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; CHECK-NEXT: cbnz w9, .LBB0_5
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; CHECK-NEXT: // %bb.3: // %for.cond
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; CHECK-NEXT: // in Loop: Header=BB0_2 Depth=1
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; CHECK-NEXT: subs x8, x8, #1
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; CHECK-NEXT: b.ne .LBB0_2
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; CHECK-NEXT: .LBB0_4:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB0_5:
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; CHECK-NEXT: mov w0, #1 // =0x1
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; CHECK-NEXT: ret
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entry:
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%cmp13 = icmp sgt i32 %c, 0
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br i1 %cmp13, label %for.body.preheader, label %return
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for.body.preheader: ; preds = %entry
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%wide.trip.count = zext i32 %c to i64
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br label %for.body
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for.cond: ; preds = %for.body
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%iv.next = add nuw nsw i64 %iv, 1
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%exitcond.not = icmp eq i64 %iv.next, %wide.trip.count
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br i1 %exitcond.not, label %return, label %for.body
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for.body: ; preds = %for.body.preheader, %for.cond
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%iv = phi i64 [ 0, %for.body.preheader ], [ %iv.next, %for.cond ]
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%arrayidx = getelementptr inbounds i32, ptr %a, i64 %iv
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%val = load i32, ptr %arrayidx, align 4
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%tobool3.not = icmp eq i32 %val, 0
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br i1 %tobool3.not, label %for.cond, label %return
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return: ; preds = %for.cond, %for.body, %entry
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%retval.1 = phi i32 [ 0, %entry ], [ 0, %for.cond ], [ 1, %for.body ]
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ret i32 %retval.1
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}
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; negative case: %arrayidx.b is not in header
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define i64 @IVIncHoist_not_all_user_in_header(i32 %c, ptr %a, ptr %b) {
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; CHECK-LABEL: IVIncHoist_not_all_user_in_header:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w0, #1
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; CHECK-NEXT: b.lt .LBB1_5
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; CHECK-NEXT: // %bb.1: // %for.body.preheader
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; CHECK-NEXT: mov x8, xzr
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; CHECK-NEXT: mov w9, w0
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; CHECK-NEXT: add x10, x1, #4
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; CHECK-NEXT: add x11, x2, #8
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; CHECK-NEXT: mov w0, #1 // =0x1
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; CHECK-NEXT: .LBB1_2: // %for.body
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldr w12, [x10, x8, lsl #2]
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; CHECK-NEXT: cbnz w12, .LBB1_7
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; CHECK-NEXT: // %bb.3: // %if.then
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; CHECK-NEXT: // in Loop: Header=BB1_2 Depth=1
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; CHECK-NEXT: ldr w12, [x11, x8, lsl #2]
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; CHECK-NEXT: cbnz w12, .LBB1_6
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; CHECK-NEXT: // %bb.4: // %for.cond
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; CHECK-NEXT: // in Loop: Header=BB1_2 Depth=1
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; CHECK-NEXT: add x8, x8, #1
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; CHECK-NEXT: cmp x9, x8
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; CHECK-NEXT: b.ne .LBB1_2
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; CHECK-NEXT: .LBB1_5:
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; CHECK-NEXT: mov x0, xzr
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB1_6: // %if.then.return.loopexit_crit_edge
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; CHECK-NEXT: add x0, x8, #3
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; CHECK-NEXT: .LBB1_7: // %return
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; CHECK-NEXT: ret
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entry:
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%cmp13 = icmp sgt i32 %c, 0
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br i1 %cmp13, label %for.body.preheader, label %return
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for.body.preheader: ; preds = %entry
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%wide.trip.count = zext i32 %c to i64
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br label %for.body
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for.cond: ; preds = %for.body
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%iv.next = add nuw nsw i64 %iv, 1
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%exitcond.not = icmp eq i64 %iv.next, %wide.trip.count
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br i1 %exitcond.not, label %return, label %for.body
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for.body: ; preds = %for.body.preheader, %for.cond
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%iv = phi i64 [ 0, %for.body.preheader ], [ %iv.next, %for.cond ]
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%iv.a = phi i64 [ 1, %for.body.preheader ], [ %iv.next.a, %for.cond ]
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%iv.b = phi i64 [ 2, %for.body.preheader ], [ %iv.next.b, %for.cond ]
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%arrayidx.a = getelementptr inbounds i32, ptr %a, i64 %iv.a
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%iv.next.a = add nuw nsw i64 %iv.a, 1
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%val.a = load i32, ptr %arrayidx.a, align 4
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%tobool3.not = icmp eq i32 %val.a, 0
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br i1 %tobool3.not, label %if.then, label %return
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if.then:
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%arrayidx.b = getelementptr inbounds i32, ptr %b, i64 %iv.b
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%iv.next.b = add nuw nsw i64 %iv.b, 1
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%val.b = load i32, ptr %arrayidx.b, align 4
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%tobool4.not = icmp eq i32 %val.b, 0
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br i1 %tobool4.not, label %for.cond, label %return
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return: ; preds = %for.cond, %for.body, %entry
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%retval.1 = phi i64 [ 0, %entry ], [ 0, %for.cond ], [ 1, %for.body ], [ %iv.next.b, %if.then ]
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ret i64 %retval.1
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}
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%struct.A = type { i32 }
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; this used to crash because the load type is struct
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define i32 @negative_test_type_is_struct(i32 %c, ptr %a, ptr %b) {
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; CHECK-LABEL: negative_test_type_is_struct:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w0, #1
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; CHECK-NEXT: b.lt .LBB2_4
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; CHECK-NEXT: // %bb.1: // %for.body.preheader
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; CHECK-NEXT: mov w8, w0
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; CHECK-NEXT: .LBB2_2: // %for.body
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldr w9, [x1]
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; CHECK-NEXT: cbnz w9, .LBB2_5
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; CHECK-NEXT: // %bb.3: // %for.cond
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; CHECK-NEXT: // in Loop: Header=BB2_2 Depth=1
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; CHECK-NEXT: subs x8, x8, #1
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; CHECK-NEXT: add x1, x1, #4
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; CHECK-NEXT: b.ne .LBB2_2
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; CHECK-NEXT: .LBB2_4:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB2_5:
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; CHECK-NEXT: mov w0, #1 // =0x1
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; CHECK-NEXT: ret
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entry:
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%cmp13 = icmp sgt i32 %c, 0
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br i1 %cmp13, label %for.body.preheader, label %return
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for.body.preheader: ; preds = %entry
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%wide.trip.count = zext i32 %c to i64
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br label %for.body
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for.cond: ; preds = %for.body
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%iv.next = add nuw nsw i64 %iv, 1
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%exitcond.not = icmp eq i64 %iv.next, %wide.trip.count
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br i1 %exitcond.not, label %return, label %for.body
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for.body: ; preds = %for.body.preheader, %for.cond
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%iv = phi i64 [ 0, %for.body.preheader ], [ %iv.next, %for.cond ]
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%arrayidx = getelementptr inbounds i32, ptr %a, i64 %iv
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%str.val = load %struct.A, ptr %arrayidx
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%val = extractvalue %struct.A %str.val, 0
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%tobool3.not = icmp eq i32 %val, 0
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br i1 %tobool3.not, label %for.cond, label %return
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return: ; preds = %for.cond, %for.body, %entry
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%retval.1 = phi i32 [ 0, %entry ], [ 0, %for.cond ], [ 1, %for.body ]
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ret i32 %retval.1
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}
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