b9808e5660
Loop unrolling tends to produce chains of `%x1 = add %x0, 1; %x2 = add %x1, 1; ...` with one add per unrolled iteration. This patch simplifies these adds to `%xN = add %x0, N` directly during unrolling, rather than waiting for InstCombine to do so. The motivation for this is that having a single add (rather than an add chain) on the induction variable makes it a simple recurrence, which we specially recognize in a number of places. This allows InstCombine to directly perform folds with that knowledge, instead of first folding the add chains, and then doing other folds in another InstCombine iteration. Due to the reduced number of InstCombine iterations, this also results in a small compile-time improvement. Differential Revision: https://reviews.llvm.org/D153540
105 lines
4.6 KiB
LLVM
105 lines
4.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=loop-unroll -unroll-count=2 -S | FileCheck %s
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; LoopUnroll should unroll this loop into one big basic block.
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define void @latch_exit(ptr nocapture %p, i64 %n) nounwind {
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; CHECK-LABEL: @latch_exit(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[MUL10:%.*]] = shl i64 [[N:%.*]], 1
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[I_013:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[TMP16_1:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr double, ptr [[P:%.*]], i64 [[I_013]]
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; CHECK-NEXT: [[TMP16:%.*]] = add nuw nsw i64 [[I_013]], 1
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr double, ptr [[P]], i64 [[TMP16]]
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; CHECK-NEXT: [[TMP4:%.*]] = load double, ptr [[ARRAYIDX]], align 8
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; CHECK-NEXT: [[TMP8:%.*]] = load double, ptr [[ARRAYIDX7]], align 8
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; CHECK-NEXT: [[MUL9:%.*]] = fmul double [[TMP8]], [[TMP4]]
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; CHECK-NEXT: store double [[MUL9]], ptr [[ARRAYIDX7]], align 8
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; CHECK-NEXT: [[ARRAYIDX7_1:%.*]] = getelementptr double, ptr [[P]], i64 [[TMP16]]
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; CHECK-NEXT: [[TMP16_1]] = add i64 [[I_013]], 2
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; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr double, ptr [[P]], i64 [[TMP16_1]]
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; CHECK-NEXT: [[TMP4_1:%.*]] = load double, ptr [[ARRAYIDX_1]], align 8
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; CHECK-NEXT: [[TMP8_1:%.*]] = load double, ptr [[ARRAYIDX7_1]], align 8
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; CHECK-NEXT: [[MUL9_1:%.*]] = fmul double [[TMP8_1]], [[TMP4_1]]
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; CHECK-NEXT: store double [[MUL9_1]], ptr [[ARRAYIDX7_1]], align 8
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; CHECK-NEXT: [[EXITCOND_1:%.*]] = icmp eq i64 [[TMP16_1]], [[MUL10]]
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; CHECK-NEXT: br i1 [[EXITCOND_1]], label [[FOR_END:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: for.end:
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; CHECK-NEXT: ret void
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;
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entry:
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%mul10 = shl i64 %n, 1
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br label %for.body
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for.body:
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%i.013 = phi i64 [ %tmp16, %for.body ], [ 0, %entry ]
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%arrayidx7 = getelementptr double, ptr %p, i64 %i.013
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%tmp16 = add i64 %i.013, 1
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%arrayidx = getelementptr double, ptr %p, i64 %tmp16
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%tmp4 = load double, ptr %arrayidx
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%tmp8 = load double, ptr %arrayidx7
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%mul9 = fmul double %tmp8, %tmp4
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store double %mul9, ptr %arrayidx7
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%exitcond = icmp eq i64 %tmp16, %mul10
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br i1 %exitcond, label %for.end, label %for.body
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for.end:
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ret void
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}
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; Same as previous test case, but with a non-latch exit. There shouldn't
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; be a conditional branch after the first block.
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define void @non_latch_exit(ptr nocapture %p, i64 %n) nounwind {
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; CHECK-LABEL: @non_latch_exit(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[MUL10:%.*]] = shl i64 [[N:%.*]], 1
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[I_013:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[TMP16_1:%.*]], [[LATCH_1:%.*]] ]
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; CHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr double, ptr [[P:%.*]], i64 [[I_013]]
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; CHECK-NEXT: [[TMP16:%.*]] = add nuw nsw i64 [[I_013]], 1
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr double, ptr [[P]], i64 [[TMP16]]
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; CHECK-NEXT: [[TMP4:%.*]] = load double, ptr [[ARRAYIDX]], align 8
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; CHECK-NEXT: [[TMP8:%.*]] = load double, ptr [[ARRAYIDX7]], align 8
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; CHECK-NEXT: [[MUL9:%.*]] = fmul double [[TMP8]], [[TMP4]]
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; CHECK-NEXT: store double [[MUL9]], ptr [[ARRAYIDX7]], align 8
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; CHECK-NEXT: br label [[LATCH:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: [[ARRAYIDX7_1:%.*]] = getelementptr double, ptr [[P]], i64 [[TMP16]]
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; CHECK-NEXT: [[TMP16_1]] = add i64 [[I_013]], 2
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; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr double, ptr [[P]], i64 [[TMP16_1]]
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; CHECK-NEXT: [[TMP4_1:%.*]] = load double, ptr [[ARRAYIDX_1]], align 8
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; CHECK-NEXT: [[TMP8_1:%.*]] = load double, ptr [[ARRAYIDX7_1]], align 8
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; CHECK-NEXT: [[MUL9_1:%.*]] = fmul double [[TMP8_1]], [[TMP4_1]]
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; CHECK-NEXT: store double [[MUL9_1]], ptr [[ARRAYIDX7_1]], align 8
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; CHECK-NEXT: [[EXITCOND_1:%.*]] = icmp eq i64 [[TMP16_1]], [[MUL10]]
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; CHECK-NEXT: br i1 [[EXITCOND_1]], label [[FOR_END:%.*]], label [[LATCH_1]]
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; CHECK: latch.1:
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; CHECK-NEXT: br label [[FOR_BODY]], !llvm.loop [[LOOP2:![0-9]+]]
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; CHECK: for.end:
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; CHECK-NEXT: ret void
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;
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entry:
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%mul10 = shl i64 %n, 1
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br label %for.body
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for.body:
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%i.013 = phi i64 [ %tmp16, %latch ], [ 0, %entry ]
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%arrayidx7 = getelementptr double, ptr %p, i64 %i.013
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%tmp16 = add i64 %i.013, 1
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%arrayidx = getelementptr double, ptr %p, i64 %tmp16
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%tmp4 = load double, ptr %arrayidx
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%tmp8 = load double, ptr %arrayidx7
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%mul9 = fmul double %tmp8, %tmp4
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store double %mul9, ptr %arrayidx7
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%exitcond = icmp eq i64 %tmp16, %mul10
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br i1 %exitcond, label %for.end, label %latch
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latch:
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br label %for.body
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for.end:
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ret void
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}
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