900bea9b1c
This is mostly NFC but some output does change due to consistently inserting into poison rather than undef and using i64 as the index type for inserts.
128 lines
5.7 KiB
LLVM
128 lines
5.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=memcpyopt -S -verify-memoryssa | FileCheck %s
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; Check that a call featuring a scalable-vector byval argument fed by a memcpy
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; doesn't crash the compiler. It previously assumed the byval type's size could
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; be represented as a known constant amount.
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define void @byval_caller(ptr %P) {
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; CHECK-LABEL: @byval_caller(
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; CHECK-NEXT: [[A:%.*]] = alloca i8, align 1
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; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[A]], ptr align 4 [[P:%.*]], i64 8, i1 false)
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; CHECK-NEXT: call void @byval_callee(ptr byval(<vscale x 1 x i8>) align 1 [[A]])
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; CHECK-NEXT: ret void
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;
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%a = alloca i8
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call void @llvm.memcpy.p0.p0.i64(ptr align 4 %a, ptr align 4 %P, i64 8, i1 false)
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call void @byval_callee(ptr align 1 byval(<vscale x 1 x i8>) %a)
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ret void
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}
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declare void @llvm.memcpy.p0.p0.i64(ptr align 4, ptr align 4, i64, i1)
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declare void @byval_callee(ptr align 1 byval(<vscale x 1 x i8>))
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; Check that two scalable-vector stores (overlapping, with a constant offset)
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; do not crash the compiler when checked whether or not they can be merged into
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; a single memset. There was previously an assumption that the stored values'
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; sizes could be represented by a known constant amount.
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define void @merge_stores_both_scalable(ptr %ptr) {
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; CHECK-LABEL: @merge_stores_both_scalable(
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; CHECK-NEXT: store <vscale x 1 x i8> zeroinitializer, ptr [[PTR:%.*]], align 1
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; CHECK-NEXT: [[PTR_NEXT:%.*]] = getelementptr i8, ptr [[PTR]], i64 1
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; CHECK-NEXT: store <vscale x 1 x i8> zeroinitializer, ptr [[PTR_NEXT]], align 1
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; CHECK-NEXT: ret void
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;
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store <vscale x 1 x i8> zeroinitializer, ptr %ptr
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%ptr.next = getelementptr i8, ptr %ptr, i64 1
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store <vscale x 1 x i8> zeroinitializer, ptr %ptr.next
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ret void
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}
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; As above, but where the base is scalable but the subsequent store(s) are not.
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define void @merge_stores_first_scalable(ptr %ptr) {
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; CHECK-LABEL: @merge_stores_first_scalable(
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; CHECK-NEXT: store <vscale x 1 x i8> zeroinitializer, ptr [[PTR:%.*]], align 1
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; CHECK-NEXT: [[PTR_NEXT:%.*]] = getelementptr i8, ptr [[PTR]], i64 1
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; CHECK-NEXT: store i8 0, ptr [[PTR_NEXT]], align 1
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; CHECK-NEXT: ret void
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;
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store <vscale x 1 x i8> zeroinitializer, ptr %ptr
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%ptr.next = getelementptr i8, ptr %ptr, i64 1
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store i8 zeroinitializer, ptr %ptr.next
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ret void
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}
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; As above, but where the base is not scalable but the subsequent store(s) are.
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define void @merge_stores_second_scalable(ptr %ptr) {
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; CHECK-LABEL: @merge_stores_second_scalable(
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; CHECK-NEXT: store i8 0, ptr [[PTR:%.*]], align 1
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; CHECK-NEXT: [[PTR_NEXT:%.*]] = getelementptr i8, ptr [[PTR]], i64 1
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; CHECK-NEXT: store <vscale x 1 x i8> zeroinitializer, ptr [[PTR_NEXT]], align 1
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; CHECK-NEXT: ret void
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;
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store i8 zeroinitializer, ptr %ptr
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%ptr.next = getelementptr i8, ptr %ptr, i64 1
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store <vscale x 1 x i8> zeroinitializer, ptr %ptr.next
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ret void
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}
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; Check that the call-slot optimization doesn't crash when encountering scalable types.
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define void @callslotoptzn(<vscale x 4 x float> %val, ptr %out) {
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; CHECK-LABEL: @callslotoptzn(
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; CHECK-NEXT: [[ALLOC:%.*]] = alloca <vscale x 4 x float>, align 16
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; CHECK-NEXT: [[IDX:%.*]] = tail call <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32()
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; CHECK-NEXT: [[STRIDE:%.*]] = getelementptr inbounds float, ptr [[ALLOC]], <vscale x 4 x i32> [[IDX]]
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; CHECK-NEXT: call void @llvm.masked.scatter.nxv4f32.nxv4p0(<vscale x 4 x float> [[VAL:%.*]], <vscale x 4 x ptr> [[STRIDE]], i32 4, <vscale x 4 x i1> shufflevector (<vscale x 4 x i1> insertelement (<vscale x 4 x i1> poison, i1 true, i64 0), <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer))
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; CHECK-NEXT: [[LI:%.*]] = load <vscale x 4 x float>, ptr [[ALLOC]], align 4
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; CHECK-NEXT: store <vscale x 4 x float> [[LI]], ptr [[OUT:%.*]], align 4
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; CHECK-NEXT: ret void
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;
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%alloc = alloca <vscale x 4 x float>, align 16
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%idx = tail call <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32()
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%stride = getelementptr inbounds float, ptr %alloc, <vscale x 4 x i32> %idx
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call void @llvm.masked.scatter.nxv4f32.nxv4p0(<vscale x 4 x float> %val, <vscale x 4 x ptr> %stride, i32 4, <vscale x 4 x i1> splat (i1 true))
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%li = load <vscale x 4 x float>, ptr %alloc, align 4
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store <vscale x 4 x float> %li, ptr %out, align 4
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ret void
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}
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%0 = type { <vscale x 8 x i8> }
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%1 = type { <vscale x 8 x i8>, <vscale x 8 x i8> }
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define void @memmove_vector(ptr %a, ptr %b) {
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; CHECK-LABEL: @memmove_vector(
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; CHECK-NEXT: [[V:%.*]] = load <vscale x 8 x i8>, ptr [[A:%.*]], align 1
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; CHECK-NEXT: store <vscale x 8 x i8> [[V]], ptr [[B:%.*]], align 1
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; CHECK-NEXT: ret void
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;
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%v = load <vscale x 8 x i8>, ptr %a, align 1
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store <vscale x 8 x i8> %v, ptr %b, align 1
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ret void
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}
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define void @memmove_agg1(ptr %a, ptr %b) {
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; CHECK-LABEL: @memmove_agg1(
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; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 8
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; CHECK-NEXT: call void @llvm.memmove.p0.p0.i64(ptr align 1 [[B:%.*]], ptr align 1 [[A:%.*]], i64 [[TMP2]], i1 false)
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; CHECK-NEXT: ret void
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;
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%v = load %0, ptr %a, align 1
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store %0 %v, ptr %b, align 1
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ret void
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}
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define void @memmove_agg2(ptr %a, ptr %b) {
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; CHECK-LABEL: @memmove_agg2(
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; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 16
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; CHECK-NEXT: call void @llvm.memmove.p0.p0.i64(ptr align 1 [[B:%.*]], ptr align 1 [[A:%.*]], i64 [[TMP2]], i1 false)
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; CHECK-NEXT: ret void
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;
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%v = load %1, ptr %a, align 1
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store %1 %v, ptr %b, align 1
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ret void
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}
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declare <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32()
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declare void @llvm.masked.scatter.nxv4f32.nxv4p0(<vscale x 4 x float> , <vscale x 4 x ptr> , i32, <vscale x 4 x i1>)
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