c34d157fc7
Swap AIC and IC neighbouring in pipeline. This looks more natural and even almost has no effect for now (three slightly touched tests of test-suite). Also this could be the first step towards merging AIC (or its part) to -O2 pipeline. After several changes in AIC (like D108091, D108201, D107766, D109515, D109236) there've been observed several regressions (like PR52078, PR52253, PR52289) that were fixed in different passes (see D111330, D112721) by extending their functionality, but these regressions were exposed since changed AIC prevents IC from making some of early optimizations. This is common problem and it should be fixed by just moving AIC after IC which looks more logically by itself: make aggressive instruction combining only after failed ordinary one. Fixes PR52289 Reviewed By: spatel, RKSimon Differential Revision: https://reviews.llvm.org/D113179
45 lines
1.0 KiB
LLVM
45 lines
1.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -O3 -S < %s | FileCheck %s
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target datalayout = "n8:16:32:64"
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define i32 @main(i32 %a) {
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; CHECK-LABEL: @main(
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; CHECK-NEXT: if.end:
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; CHECK-NEXT: ret i32 0
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;
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%inc = add nsw i32 %a, 1
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%and = and i32 %inc, 8
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%conv = trunc i32 %and to i8
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%call = call fastcc i8 @a(i8 %conv, i32 7)
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%conv1 = sext i8 %call to i64
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%call2 = call fastcc i64 @d(i64 %conv1)
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%mul = mul nsw i64 %call2, 20681
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%conv3 = trunc i64 %mul to i16
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%conv4 = sext i16 %conv3 to i32
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%xor = xor i32 %conv4, 1
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%tobool = icmp ne i32 %xor, 0
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br i1 %tobool, label %if.end, label %if.then
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if.then:
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call void undef()
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br label %if.end
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if.end:
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%call5 = call fastcc i8 @a(i8 0, i32 0)
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ret i32 0
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}
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define internal fastcc i8 @a(i8 %h, i32 %i) {
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%t0 = zext i8 %h to i32
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%cmp = icmp sgt i32 %t0, %i
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%shl = shl i32 %t0, %i
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%cond = select i1 %cmp, i32 %t0, i32 %shl
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%conv4 = trunc i32 %cond to i8
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ret i8 %conv4
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}
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define internal fastcc i64 @d(i64 %h) {
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ret i64 %h
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}
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