1c55cc600e
Required manually running update_test_checks: AArch64/hoisting-sinking-required-for-vectorization.ll AArch64/peel-multiple-unreachable-exits-for-vectorization.ll ARM/arm_mult_q15.ll X86/hoist-load-of-baseptr.ll X86/spurious-peeling.ll
38 lines
1.0 KiB
LLVM
38 lines
1.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -O3 -S < %s | FileCheck %s
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; RUN: opt -passes='default<O3>' -S < %s | FileCheck %s
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define void @PR45682(i32 %x, i32 %y) {
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; CHECK-LABEL: @PR45682(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[Y:%.*]], 0
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[CMP]])
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; CHECK-NEXT: ret void
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;
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entry:
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%x.addr = alloca i32, align 4
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%y.addr = alloca i32, align 4
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store i32 %x, ptr %x.addr, align 4
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store i32 %y, ptr %y.addr, align 4
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%0 = load i32, ptr %y.addr, align 4
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%cmp = icmp sgt i32 %0, 0
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call void @llvm.assume(i1 %cmp)
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%1 = load i32, ptr %y.addr, align 4
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%2 = load i32, ptr %x.addr, align 4
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%add = add nsw i32 %2, %1
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store i32 %add, ptr %x.addr, align 4
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%3 = load i32, ptr %x.addr, align 4
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%cmp1 = icmp eq i32 %3, -2147483648
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br i1 %cmp1, label %if.then, label %if.end
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if.then:
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call void @v()
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br label %if.end
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if.end:
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ret void
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}
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declare void @v()
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declare void @llvm.assume(i1)
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