72121a20cd
This patch updates SCCP to use the value ranges of AddInst operands to try to prove the AddInst does not overflow in the signed sense and adds the NSW flag. The reasoning is done with makeGuaranteedNoWrapRegion (thanks @nikic for point it out!). Follow-ups will include extending this to more OverflowingBinaryOperators. Depends on D142387. Reviewed By: nikic Differential Revision: https://reviews.llvm.org/D142390
141 lines
4.9 KiB
LLVM
141 lines
4.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature
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; RUN: opt -passes=ipsccp -S %s -o -| FileCheck %s
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define void @caller.1(ptr %arg) {
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; CHECK-LABEL: define {{[^@]+}}@caller.1
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; CHECK-SAME: (ptr [[ARG:%.*]]) {
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; CHECK-NEXT: [[R_1:%.*]] = tail call i32 @callee.1(i32 4)
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; CHECK-NEXT: [[R_2:%.*]] = tail call i32 @callee.1(i32 2)
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; CHECK-NEXT: call void @use(i32 20)
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; CHECK-NEXT: ret void
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;
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%r.1 = tail call i32 @callee.1(i32 4)
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%r.2 = tail call i32 @callee.1(i32 2)
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%r.3 = add i32 %r.1, %r.2
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call void @use(i32 %r.3)
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ret void
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}
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define internal i32 @callee.1(i32 %arg) {
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; CHECK-LABEL: define {{[^@]+}}@callee.1
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; CHECK-SAME: (i32 [[ARG:%.*]]) {
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; CHECK-NEXT: [[SEL:%.*]] = select i1 false, i32 16, i32 [[ARG]]
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; CHECK-NEXT: br label [[BB10:%.*]]
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; CHECK: bb10:
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; CHECK-NEXT: ret i32 undef
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;
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%c.1 = icmp slt i32 %arg, 0
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%sel = select i1 %c.1, i32 16, i32 %arg
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%c.2 = icmp eq i32 %sel, 0
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br i1 %c.2, label %bb12, label %bb10
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bb10: ; preds = %bb8
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ret i32 10
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bb12: ; preds = %bb8, %bb3, %bb
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ret i32 12
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}
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declare void @use(i32)
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define internal i1 @f1(i32 %x, i32 %y, i1 %cmp) {
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; CHECK-LABEL: define {{[^@]+}}@f1
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; CHECK-SAME: (i32 [[X:%.*]], i32 [[Y:%.*]], i1 [[CMP:%.*]]) {
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; CHECK-NEXT: [[SEL_1:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[Y]]
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; CHECK-NEXT: [[C_2:%.*]] = icmp sgt i32 [[SEL_1]], 100
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; CHECK-NEXT: [[C_3:%.*]] = icmp eq i32 [[SEL_1]], 50
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; CHECK-NEXT: [[RES_1:%.*]] = add nuw nsw i1 false, [[C_2]]
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; CHECK-NEXT: [[RES_2:%.*]] = add i1 [[RES_1]], [[C_3]]
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; CHECK-NEXT: [[RES_3:%.*]] = add nuw nsw i1 [[RES_2]], false
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; CHECK-NEXT: ret i1 [[RES_3]]
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;
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%sel.1 = select i1 %cmp, i32 %x, i32 %y
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%c.1 = icmp sgt i32 %sel.1, 300
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%c.2 = icmp sgt i32 %sel.1, 100
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%c.3 = icmp eq i32 %sel.1, 50
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%c.4 = icmp slt i32 %sel.1, 9
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%res.1 = add i1 %c.1, %c.2
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%res.2 = add i1 %res.1, %c.3
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%res.3 = add i1 %res.2, %c.4
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ret i1 %res.3
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}
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define i1 @caller1(i1 %cmp) {
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; CHECK-LABEL: define {{[^@]+}}@caller1
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; CHECK-SAME: (i1 [[CMP:%.*]]) {
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; CHECK-NEXT: [[CALL_1:%.*]] = tail call i1 @f1(i32 10, i32 100, i1 [[CMP]])
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; CHECK-NEXT: [[CALL_2:%.*]] = tail call i1 @f1(i32 20, i32 200, i1 [[CMP]])
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; CHECK-NEXT: [[RES:%.*]] = and i1 [[CALL_1]], [[CALL_2]]
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; CHECK-NEXT: ret i1 [[RES]]
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;
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%call.1 = tail call i1 @f1(i32 10, i32 100, i1 %cmp)
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%call.2 = tail call i1 @f1(i32 20, i32 200, i1 %cmp)
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%res = and i1 %call.1, %call.2
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ret i1 %res
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}
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define i1 @f2(i32 %x, i32 %y, i1 %cmp) {
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; CHECK-LABEL: define {{[^@]+}}@f2
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; CHECK-SAME: (i32 [[X:%.*]], i32 [[Y:%.*]], i1 [[CMP:%.*]]) {
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; CHECK-NEXT: [[SEL_1:%.*]] = select i1 [[CMP]], i32 [[X]], i32 [[Y]]
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; CHECK-NEXT: [[C_1:%.*]] = icmp sgt i32 [[SEL_1]], 300
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; CHECK-NEXT: [[C_2:%.*]] = icmp sgt i32 [[SEL_1]], 100
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; CHECK-NEXT: [[C_3:%.*]] = icmp eq i32 [[SEL_1]], 50
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; CHECK-NEXT: [[C_4:%.*]] = icmp slt i32 [[SEL_1]], 9
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; CHECK-NEXT: [[RES_1:%.*]] = add i1 [[C_1]], [[C_2]]
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; CHECK-NEXT: [[RES_2:%.*]] = add i1 [[RES_1]], [[C_3]]
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; CHECK-NEXT: [[RES_3:%.*]] = add i1 [[RES_2]], [[C_4]]
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; CHECK-NEXT: ret i1 [[RES_3]]
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;
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%sel.1 = select i1 %cmp, i32 %x, i32 %y
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%c.1 = icmp sgt i32 %sel.1, 300
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%c.2 = icmp sgt i32 %sel.1, 100
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%c.3 = icmp eq i32 %sel.1, 50
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%c.4 = icmp slt i32 %sel.1, 9
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%res.1 = add i1 %c.1, %c.2
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%res.2 = add i1 %res.1, %c.3
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%res.3 = add i1 %res.2, %c.4
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ret i1 %res.3
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}
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define i1 @caller2(i32 %y, i1 %cmp) {
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; CHECK-LABEL: define {{[^@]+}}@caller2
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; CHECK-SAME: (i32 [[Y:%.*]], i1 [[CMP:%.*]]) {
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; CHECK-NEXT: [[CALL_1:%.*]] = tail call i1 @f2(i32 10, i32 [[Y]], i1 [[CMP]])
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; CHECK-NEXT: [[CALL_2:%.*]] = tail call i1 @f2(i32 20, i32 [[Y]], i1 [[CMP]])
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; CHECK-NEXT: [[RES:%.*]] = and i1 [[CALL_1]], [[CALL_2]]
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; CHECK-NEXT: ret i1 [[RES]]
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;
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%call.1 = tail call i1 @f2(i32 10, i32 %y, i1 %cmp)
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%call.2 = tail call i1 @f2(i32 20, i32 %y, i1 %cmp)
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%res = and i1 %call.1, %call.2
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ret i1 %res
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}
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@GV = common global i32 0, align 4
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define i32 @f3_constantexpr_cond(i32 %x, i32 %y) {
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; CHECK-LABEL: define {{[^@]+}}@f3_constantexpr_cond
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; CHECK-SAME: (i32 [[X:%.*]], i32 [[Y:%.*]]) {
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; CHECK-NEXT: [[SEL_1:%.*]] = select i1 icmp eq (ptr @f3_constantexpr_cond, ptr @GV), i32 [[X]], i32 [[Y]]
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; CHECK-NEXT: ret i32 [[SEL_1]]
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;
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%sel.1 = select i1 icmp eq (ptr @f3_constantexpr_cond, ptr @GV), i32 %x, i32 %y
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ret i32 %sel.1
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}
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define i32 @caller3(i32 %y) {
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; CHECK-LABEL: define {{[^@]+}}@caller3
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; CHECK-SAME: (i32 [[Y:%.*]]) {
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; CHECK-NEXT: [[CALL_1:%.*]] = tail call i32 @f3_constantexpr_cond(i32 10, i32 [[Y]])
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; CHECK-NEXT: [[CALL_2:%.*]] = tail call i32 @f3_constantexpr_cond(i32 20, i32 [[Y]])
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; CHECK-NEXT: [[RES:%.*]] = and i32 [[CALL_1]], [[CALL_2]]
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; CHECK-NEXT: ret i32 [[RES]]
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;
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%call.1 = tail call i32 @f3_constantexpr_cond(i32 10, i32 %y)
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%call.2 = tail call i32 @f3_constantexpr_cond(i32 20, i32 %y)
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%res = and i32 %call.1, %call.2
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ret i32 %res
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}
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