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clang-p2996/llvm/test/Transforms/SLPVectorizer/AArch64/matmul.ll
David Green 2a859b2014 [AArch64] Change the cost of vector insert/extract to 2 
The cost of vector instructions has always been high under AArch64, in order to
add a high cost for inserts/extracts, shuffles and scalarization. This is a
conservative approach to limit the scope of unusual SLP vectorization where the
codegen ends up being quite poor, but has always been higher than the correct
costs would be for any specific core.

This relaxes that, reducing the vector insert/extract cost from 3 to 2. It is a
generalization of D142359 to all AArch64 cpus. The ScalarizationOverhead is
also overridden for integer vector at the same time, to remove the effect of
lane 0 being considered free for integer vectors (something that should only be
true for float when scalarizing).

The lower insert/extract cost will reduce the cost of insert, extracts,
shuffling and scalarization. The adjustments of ScalaizationOverhead will
increase the cost on integer, especially for small vectors. The end result will
be lower cost for float and long-integer types, some higher cost for some
smaller vectors. This, along with the raw insert/extract cost being lower, will
generally mean more vectorization from the Loop and SLP vectorizer.

We may end up regretting this, as that vectorization is not always profitable.
In all the benchmarking I have done this is generally an improvement in the
overall performance, and I've attempted to address the places where it wasn't
with other costmodel adjustments.

Differential Revision: https://reviews.llvm.org/D155459
2023-07-28 21:26:50 +01:00

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=aarch64-unknown-unknown -mcpu=cortex-a53 | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
; This test is reduced from the matrix multiplication benchmark in the test-suite:
; https://github.com/llvm/llvm-test-suite/tree/main/SingleSource/Benchmarks/Misc/matmul_f64_4x4.c
; The operations here are expected to be vectorized to <2 x double>.
; Otherwise, performance will suffer on Cortex-A53.
define void @wrap_mul4(ptr nocapture %Out, ptr nocapture readonly %A, ptr nocapture readonly %B) {
; CHECK-LABEL: @wrap_mul4(
; CHECK-NEXT: [[TEMP:%.*]] = load double, ptr [[A:%.*]], align 8
; CHECK-NEXT: [[ARRAYIDX5_I:%.*]] = getelementptr inbounds [2 x double], ptr [[A]], i64 0, i64 1
; CHECK-NEXT: [[TEMP2:%.*]] = load double, ptr [[ARRAYIDX5_I]], align 8
; CHECK-NEXT: [[ARRAYIDX7_I:%.*]] = getelementptr inbounds [4 x double], ptr [[B:%.*]], i64 1, i64 0
; CHECK-NEXT: [[ARRAYIDX25_I:%.*]] = getelementptr inbounds [4 x double], ptr [[B]], i64 0, i64 2
; CHECK-NEXT: [[ARRAYIDX30_I:%.*]] = getelementptr inbounds [4 x double], ptr [[B]], i64 1, i64 2
; CHECK-NEXT: [[ARRAYIDX47_I:%.*]] = getelementptr inbounds [2 x double], ptr [[A]], i64 1, i64 0
; CHECK-NEXT: [[TEMP10:%.*]] = load double, ptr [[ARRAYIDX47_I]], align 8
; CHECK-NEXT: [[ARRAYIDX52_I:%.*]] = getelementptr inbounds [2 x double], ptr [[A]], i64 1, i64 1
; CHECK-NEXT: [[TEMP11:%.*]] = load double, ptr [[ARRAYIDX52_I]], align 8
; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[B]], align 8
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[TEMP]], i32 0
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = fmul <2 x double> [[TMP3]], [[TMP1]]
; CHECK-NEXT: [[TMP5:%.*]] = load <2 x double>, ptr [[ARRAYIDX7_I]], align 8
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x double> poison, double [[TEMP2]], i32 0
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x double> [[TMP6]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP8:%.*]] = fmul <2 x double> [[TMP7]], [[TMP5]]
; CHECK-NEXT: [[TMP9:%.*]] = fadd <2 x double> [[TMP4]], [[TMP8]]
; CHECK-NEXT: [[RES_I_SROA_5_0_OUT2_I_SROA_IDX4:%.*]] = getelementptr inbounds double, ptr [[OUT:%.*]], i64 2
; CHECK-NEXT: [[TMP10:%.*]] = load <2 x double>, ptr [[ARRAYIDX25_I]], align 8
; CHECK-NEXT: [[TMP11:%.*]] = fmul <2 x double> [[TMP3]], [[TMP10]]
; CHECK-NEXT: [[TMP12:%.*]] = load <2 x double>, ptr [[ARRAYIDX30_I]], align 8
; CHECK-NEXT: [[TMP13:%.*]] = fmul <2 x double> [[TMP7]], [[TMP12]]
; CHECK-NEXT: [[TMP14:%.*]] = fadd <2 x double> [[TMP11]], [[TMP13]]
; CHECK-NEXT: store <2 x double> [[TMP9]], ptr [[OUT]], align 8
; CHECK-NEXT: store <2 x double> [[TMP14]], ptr [[RES_I_SROA_5_0_OUT2_I_SROA_IDX4]], align 8
; CHECK-NEXT: [[RES_I_SROA_7_0_OUT2_I_SROA_IDX8:%.*]] = getelementptr inbounds double, ptr [[OUT]], i64 4
; CHECK-NEXT: [[TMP15:%.*]] = insertelement <2 x double> poison, double [[TEMP10]], i32 0
; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <2 x double> [[TMP15]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP17:%.*]] = fmul <2 x double> [[TMP1]], [[TMP16]]
; CHECK-NEXT: [[TMP18:%.*]] = insertelement <2 x double> poison, double [[TEMP11]], i32 0
; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <2 x double> [[TMP18]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP20:%.*]] = fmul <2 x double> [[TMP5]], [[TMP19]]
; CHECK-NEXT: [[TMP21:%.*]] = fadd <2 x double> [[TMP17]], [[TMP20]]
; CHECK-NEXT: store <2 x double> [[TMP21]], ptr [[RES_I_SROA_7_0_OUT2_I_SROA_IDX8]], align 8
; CHECK-NEXT: [[RES_I_SROA_9_0_OUT2_I_SROA_IDX12:%.*]] = getelementptr inbounds double, ptr [[OUT]], i64 6
; CHECK-NEXT: [[TMP22:%.*]] = fmul <2 x double> [[TMP10]], [[TMP16]]
; CHECK-NEXT: [[TMP23:%.*]] = fmul <2 x double> [[TMP12]], [[TMP19]]
; CHECK-NEXT: [[TMP24:%.*]] = fadd <2 x double> [[TMP22]], [[TMP23]]
; CHECK-NEXT: store <2 x double> [[TMP24]], ptr [[RES_I_SROA_9_0_OUT2_I_SROA_IDX12]], align 8
; CHECK-NEXT: ret void
;
%temp = load double, ptr %A, align 8
%temp1 = load double, ptr %B, align 8
%mul.i = fmul double %temp, %temp1
%arrayidx5.i = getelementptr inbounds [2 x double], ptr %A, i64 0, i64 1
%temp2 = load double, ptr %arrayidx5.i, align 8
%arrayidx7.i = getelementptr inbounds [4 x double], ptr %B, i64 1, i64 0
%temp3 = load double, ptr %arrayidx7.i, align 8
%mul8.i = fmul double %temp2, %temp3
%add.i = fadd double %mul.i, %mul8.i
%arrayidx13.i = getelementptr inbounds [4 x double], ptr %B, i64 0, i64 1
%temp4 = load double, ptr %arrayidx13.i, align 8
%mul14.i = fmul double %temp, %temp4
%arrayidx18.i = getelementptr inbounds [4 x double], ptr %B, i64 1, i64 1
%temp5 = load double, ptr %arrayidx18.i, align 8
%mul19.i = fmul double %temp2, %temp5
%add20.i = fadd double %mul14.i, %mul19.i
%arrayidx25.i = getelementptr inbounds [4 x double], ptr %B, i64 0, i64 2
%temp6 = load double, ptr %arrayidx25.i, align 8
%mul26.i = fmul double %temp, %temp6
%arrayidx30.i = getelementptr inbounds [4 x double], ptr %B, i64 1, i64 2
%temp7 = load double, ptr %arrayidx30.i, align 8
%mul31.i = fmul double %temp2, %temp7
%add32.i = fadd double %mul26.i, %mul31.i
%arrayidx37.i = getelementptr inbounds [4 x double], ptr %B, i64 0, i64 3
%temp8 = load double, ptr %arrayidx37.i, align 8
%mul38.i = fmul double %temp, %temp8
%arrayidx42.i = getelementptr inbounds [4 x double], ptr %B, i64 1, i64 3
%temp9 = load double, ptr %arrayidx42.i, align 8
%mul43.i = fmul double %temp2, %temp9
%add44.i = fadd double %mul38.i, %mul43.i
%arrayidx47.i = getelementptr inbounds [2 x double], ptr %A, i64 1, i64 0
%temp10 = load double, ptr %arrayidx47.i, align 8
%mul50.i = fmul double %temp1, %temp10
%arrayidx52.i = getelementptr inbounds [2 x double], ptr %A, i64 1, i64 1
%temp11 = load double, ptr %arrayidx52.i, align 8
%mul55.i = fmul double %temp3, %temp11
%add56.i = fadd double %mul50.i, %mul55.i
%mul62.i = fmul double %temp4, %temp10
%mul67.i = fmul double %temp5, %temp11
%add68.i = fadd double %mul62.i, %mul67.i
%mul74.i = fmul double %temp6, %temp10
%mul79.i = fmul double %temp7, %temp11
%add80.i = fadd double %mul74.i, %mul79.i
%mul86.i = fmul double %temp8, %temp10
%mul91.i = fmul double %temp9, %temp11
%add92.i = fadd double %mul86.i, %mul91.i
store double %add.i, ptr %Out, align 8
%Res.i.sroa.4.0.Out2.i.sroa_idx2 = getelementptr inbounds double, ptr %Out, i64 1
store double %add20.i, ptr %Res.i.sroa.4.0.Out2.i.sroa_idx2, align 8
%Res.i.sroa.5.0.Out2.i.sroa_idx4 = getelementptr inbounds double, ptr %Out, i64 2
store double %add32.i, ptr %Res.i.sroa.5.0.Out2.i.sroa_idx4, align 8
%Res.i.sroa.6.0.Out2.i.sroa_idx6 = getelementptr inbounds double, ptr %Out, i64 3
store double %add44.i, ptr %Res.i.sroa.6.0.Out2.i.sroa_idx6, align 8
%Res.i.sroa.7.0.Out2.i.sroa_idx8 = getelementptr inbounds double, ptr %Out, i64 4
store double %add56.i, ptr %Res.i.sroa.7.0.Out2.i.sroa_idx8, align 8
%Res.i.sroa.8.0.Out2.i.sroa_idx10 = getelementptr inbounds double, ptr %Out, i64 5
store double %add68.i, ptr %Res.i.sroa.8.0.Out2.i.sroa_idx10, align 8
%Res.i.sroa.9.0.Out2.i.sroa_idx12 = getelementptr inbounds double, ptr %Out, i64 6
store double %add80.i, ptr %Res.i.sroa.9.0.Out2.i.sroa_idx12, align 8
%Res.i.sroa.10.0.Out2.i.sroa_idx14 = getelementptr inbounds double, ptr %Out, i64 7
store double %add92.i, ptr %Res.i.sroa.10.0.Out2.i.sroa_idx14, align 8
ret void
}
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