5adfad254e
SLP includes analysis for the minimum bitwidth, the actual integer operations can be emitted. It allows to reduce register pressure and improve perf. Currently, it includes only cost model and the next transformation relies on InstructionCombiner. Better to do it directly in SLP, it allows to reduce compile time and fix cost model issues.
98 lines
3.8 KiB
LLVM
98 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=slp-vectorizer -S | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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@d = internal unnamed_addr global i32 5, align 4
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define dso_local void @l() local_unnamed_addr {
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; CHECK-LABEL: @l(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: br label [[BB1:%.*]]
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; CHECK: bb1:
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; CHECK-NEXT: [[TMP0:%.*]] = phi <2 x i16> [ undef, [[BB:%.*]] ], [ [[TMP9:%.*]], [[BB25:%.*]] ]
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; CHECK-NEXT: br i1 undef, label [[BB3:%.*]], label [[BB11:%.*]]
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; CHECK: bb3:
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; CHECK-NEXT: [[I4:%.*]] = zext i1 undef to i32
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; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i16> [[TMP0]], undef
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ugt <2 x i16> [[TMP1]], <i16 8, i16 8>
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; CHECK-NEXT: br label [[BB25]]
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; CHECK: bb11:
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; CHECK-NEXT: [[I12:%.*]] = zext i1 undef to i32
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; CHECK-NEXT: [[TMP3:%.*]] = xor <2 x i16> [[TMP0]], undef
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; CHECK-NEXT: [[TMP4:%.*]] = sext <2 x i16> [[TMP3]] to <2 x i64>
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; CHECK-NEXT: [[TMP5:%.*]] = icmp ule <2 x i64> undef, [[TMP4]]
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; CHECK-NEXT: [[TMP6:%.*]] = zext <2 x i1> [[TMP5]] to <2 x i32>
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; CHECK-NEXT: [[TMP7:%.*]] = icmp ult <2 x i32> undef, [[TMP6]]
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; CHECK-NEXT: br label [[BB25]]
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; CHECK: bb25:
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; CHECK-NEXT: [[I28:%.*]] = phi i32 [ [[I12]], [[BB11]] ], [ [[I4]], [[BB3]] ]
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; CHECK-NEXT: [[TMP8:%.*]] = phi <2 x i1> [ [[TMP7]], [[BB11]] ], [ [[TMP2]], [[BB3]] ]
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; CHECK-NEXT: [[TMP9]] = phi <2 x i16> [ [[TMP3]], [[BB11]] ], [ [[TMP1]], [[BB3]] ]
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; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x i1> [[TMP8]], i32 0
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; CHECK-NEXT: [[TMP11:%.*]] = zext i1 [[TMP10]] to i32
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; CHECK-NEXT: [[I31:%.*]] = and i32 undef, [[TMP11]]
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; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x i1> [[TMP8]], i32 1
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; CHECK-NEXT: [[TMP13:%.*]] = zext i1 [[TMP12]] to i32
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; CHECK-NEXT: [[I32:%.*]] = and i32 [[I31]], [[TMP13]]
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; CHECK-NEXT: [[I33:%.*]] = and i32 [[I32]], [[I28]]
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; CHECK-NEXT: br i1 undef, label [[BB34:%.*]], label [[BB1]]
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; CHECK: bb34:
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; CHECK-NEXT: [[I35:%.*]] = phi i32 [ [[I33]], [[BB25]] ]
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; CHECK-NEXT: br label [[BB36:%.*]]
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; CHECK: bb36:
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; CHECK-NEXT: store i32 [[I35]], ptr @d, align 4
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; CHECK-NEXT: ret void
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;
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bb:
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br label %bb1
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bb1: ; preds = %bb25, %bb
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%i = phi i16 [ undef, %bb ], [ %i29, %bb25 ]
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%i2 = phi i16 [ undef, %bb ], [ %i30, %bb25 ]
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br i1 undef, label %bb3, label %bb11
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bb3: ; preds = %bb1
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%i4 = zext i1 undef to i32
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%i5 = xor i16 %i2, undef
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%i6 = icmp ugt i16 %i5, 8
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%i7 = zext i1 %i6 to i32
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%i8 = xor i16 %i, undef
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%i9 = icmp ugt i16 %i8, 8
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%i10 = zext i1 %i9 to i32
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br label %bb25
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bb11: ; preds = %bb1
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%i12 = zext i1 undef to i32
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%i13 = xor i16 %i2, undef
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%i14 = sext i16 %i13 to i64
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%i15 = icmp ule i64 undef, %i14
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%i16 = zext i1 %i15 to i32
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%i17 = icmp ult i32 undef, %i16
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%i18 = zext i1 %i17 to i32
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%i19 = xor i16 %i, undef
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%i20 = sext i16 %i19 to i64
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%i21 = icmp ule i64 undef, %i20
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%i22 = zext i1 %i21 to i32
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%i23 = icmp ult i32 undef, %i22
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%i24 = zext i1 %i23 to i32
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br label %bb25
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bb25: ; preds = %bb11, %bb3
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%i26 = phi i32 [ %i24, %bb11 ], [ %i10, %bb3 ]
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%i27 = phi i32 [ %i18, %bb11 ], [ %i7, %bb3 ]
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%i28 = phi i32 [ %i12, %bb11 ], [ %i4, %bb3 ]
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%i29 = phi i16 [ %i19, %bb11 ], [ %i8, %bb3 ]
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%i30 = phi i16 [ %i13, %bb11 ], [ %i5, %bb3 ]
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%i31 = and i32 undef, %i26
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%i32 = and i32 %i31, %i27
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%i33 = and i32 %i32, %i28
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br i1 undef, label %bb34, label %bb1
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bb34: ; preds = %bb25
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%i35 = phi i32 [ %i33, %bb25 ]
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br label %bb36
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bb36: ; preds = %bb34
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store i32 %i35, ptr @d, align 4
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ret void
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}
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