eecb99c5f6
These tests rely on SCEV looking recognizing an "or" with no common bits as an "add". Add the disjoint flag to relevant or instructions in preparation for switching SCEV to use the flag instead of the ValueTracking query. The IR with disjoint flag matches what InstCombine would produce.
60 lines
3.3 KiB
LLVM
60 lines
3.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=nvptx64-nvidia-cuda -mcpu=sm_70 | FileCheck %s
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; RUN: opt < %s -passes=slp-vectorizer -S -mtriple=nvptx64-nvidia-cuda -mcpu=sm_40 | FileCheck %s -check-prefix=NOVECTOR
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define void @fusion(ptr noalias nocapture align 256 dereferenceable(19267584) %arg, ptr noalias nocapture readonly align 256 dereferenceable(19267584) %arg1, i32 %arg2, i32 %arg3) local_unnamed_addr #0 {
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; CHECK-LABEL: @fusion(
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; CHECK-NEXT: [[TMP:%.*]] = shl nuw nsw i32 [[ARG2:%.*]], 6
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; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP]], [[ARG3:%.*]]
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; CHECK-NEXT: [[TMP5:%.*]] = shl nuw nsw i32 [[TMP4]], 2
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; CHECK-NEXT: [[TMP6:%.*]] = zext i32 [[TMP5]] to i64
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; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds half, ptr [[ARG1:%.*]], i64 [[TMP6]]
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; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds half, ptr [[ARG:%.*]], i64 [[TMP6]]
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; CHECK-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr [[TMP11]], align 8
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; CHECK-NEXT: [[TMP2:%.*]] = fmul fast <2 x half> [[TMP1]], <half 0xH5380, half 0xH5380>
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; CHECK-NEXT: [[TMP3:%.*]] = fadd fast <2 x half> [[TMP2]], <half 0xH57F0, half 0xH57F0>
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; CHECK-NEXT: store <2 x half> [[TMP3]], ptr [[TMP16]], align 8
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; CHECK-NEXT: ret void
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;
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; NOVECTOR-LABEL: @fusion(
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; NOVECTOR-NEXT: [[TMP:%.*]] = shl nuw nsw i32 [[ARG2:%.*]], 6
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; NOVECTOR-NEXT: [[TMP4:%.*]] = or i32 [[TMP]], [[ARG3:%.*]]
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; NOVECTOR-NEXT: [[TMP5:%.*]] = shl nuw nsw i32 [[TMP4]], 2
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; NOVECTOR-NEXT: [[TMP6:%.*]] = zext i32 [[TMP5]] to i64
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; NOVECTOR-NEXT: [[TMP7:%.*]] = or disjoint i64 [[TMP6]], 1
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; NOVECTOR-NEXT: [[TMP11:%.*]] = getelementptr inbounds half, ptr [[ARG1:%.*]], i64 [[TMP6]]
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; NOVECTOR-NEXT: [[TMP12:%.*]] = load half, ptr [[TMP11]], align 8
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; NOVECTOR-NEXT: [[TMP13:%.*]] = fmul fast half [[TMP12]], 0xH5380
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; NOVECTOR-NEXT: [[TMP14:%.*]] = fadd fast half [[TMP13]], 0xH57F0
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; NOVECTOR-NEXT: [[TMP16:%.*]] = getelementptr inbounds half, ptr [[ARG:%.*]], i64 [[TMP6]]
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; NOVECTOR-NEXT: store half [[TMP14]], ptr [[TMP16]], align 8
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; NOVECTOR-NEXT: [[TMP17:%.*]] = getelementptr inbounds half, ptr [[ARG1]], i64 [[TMP7]]
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; NOVECTOR-NEXT: [[TMP18:%.*]] = load half, ptr [[TMP17]], align 2
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; NOVECTOR-NEXT: [[TMP19:%.*]] = fmul fast half [[TMP18]], 0xH5380
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; NOVECTOR-NEXT: [[TMP20:%.*]] = fadd fast half [[TMP19]], 0xH57F0
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; NOVECTOR-NEXT: [[TMP21:%.*]] = getelementptr inbounds half, ptr [[ARG]], i64 [[TMP7]]
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; NOVECTOR-NEXT: store half [[TMP20]], ptr [[TMP21]], align 2
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; NOVECTOR-NEXT: ret void
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;
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%tmp = shl nuw nsw i32 %arg2, 6
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%tmp4 = or i32 %tmp, %arg3
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%tmp5 = shl nuw nsw i32 %tmp4, 2
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%tmp6 = zext i32 %tmp5 to i64
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%tmp7 = or disjoint i64 %tmp6, 1
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%tmp11 = getelementptr inbounds half, ptr %arg1, i64 %tmp6
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%tmp12 = load half, ptr %tmp11, align 8
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%tmp13 = fmul fast half %tmp12, 0xH5380
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%tmp14 = fadd fast half %tmp13, 0xH57F0
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%tmp16 = getelementptr inbounds half, ptr %arg, i64 %tmp6
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store half %tmp14, ptr %tmp16, align 8
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%tmp17 = getelementptr inbounds half, ptr %arg1, i64 %tmp7
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%tmp18 = load half, ptr %tmp17, align 2
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%tmp19 = fmul fast half %tmp18, 0xH5380
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%tmp20 = fadd fast half %tmp19, 0xH57F0
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%tmp21 = getelementptr inbounds half, ptr %arg, i64 %tmp7
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store half %tmp20, ptr %tmp21, align 2
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ret void
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}
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attributes #0 = { nounwind }
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