cd29126b63
If the node has cmp instruction with 3 or more different but swappable predicates, need to keep same kind of main/alternate opcodes to avoid incorrect detection of opcodes after reordering. Reordering changes the order and we may erroneously consider swappable opcodes as non-compatible/alternate, which may lead to a later compiler crash. Reviewers: RKSimon Reviewed By: RKSimon Pull Request: https://github.com/llvm/llvm-project/pull/87267
52 lines
2.5 KiB
LLVM
52 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
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define i32 @test(ptr %sptr, i64 %0) {
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; CHECK-LABEL: define i32 @test(
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; CHECK-SAME: ptr [[SPTR:%.*]], i64 [[TMP0:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CONV_I:%.*]] = trunc i64 [[TMP0]] to i32
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; CHECK-NEXT: [[IV2:%.*]] = getelementptr i8, ptr [[SPTR]], i64 4
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; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[IV2]], align 4
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; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[CONV_I]], i32 1
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; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 1>
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; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 1, i32 poison>
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; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP4]], <4 x i32> <i32 poison, i32 poison, i32 poison, i32 0>, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
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; CHECK-NEXT: [[TMP6:%.*]] = icmp sle <4 x i32> [[TMP3]], [[TMP5]]
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; CHECK-NEXT: [[TMP7:%.*]] = icmp slt <4 x i32> [[TMP3]], [[TMP5]]
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; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i1> [[TMP6]], <4 x i1> [[TMP7]], <4 x i32> <i32 4, i32 5, i32 2, i32 7>
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; CHECK-NEXT: [[TMP9:%.*]] = icmp eq <4 x i32> [[TMP1]], zeroinitializer
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; CHECK-NEXT: [[TMP10:%.*]] = or <4 x i1> [[TMP9]], [[TMP8]]
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; CHECK-NEXT: [[TMP11:%.*]] = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> [[TMP10]])
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; CHECK-NEXT: [[AND33:%.*]] = zext i1 [[TMP11]] to i32
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; CHECK-NEXT: ret i32 [[AND33]]
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;
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entry:
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%conv.i = trunc i64 %0 to i32
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%iv2 = getelementptr i8, ptr %sptr, i64 4
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%1 = load i32, ptr %iv2, align 4
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%cmp11 = icmp slt i32 %1, %conv.i
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%cmp.i57 = icmp eq i32 %1, 0
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%or.i5977 = or i1 %cmp.i57, %cmp11
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%iv4 = getelementptr i8, ptr %sptr, i64 12
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%2 = load i32, ptr %iv4, align 4
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%cmp16 = icmp sle i32 %2, %conv.i
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%cmp.i62 = icmp eq i32 %2, 0
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%or.i6478 = or i1 %cmp.i62, %cmp16
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%iv3 = getelementptr i8, ptr %sptr, i64 8
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%3 = load i32, ptr %iv3, align 8
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%cmp21 = icmp sgt i32 %3, %conv.i
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%cmp.i67 = icmp eq i32 %3, 0
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%or.i6979 = or i1 %cmp.i67, %cmp21
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%iv5 = getelementptr i8, ptr %sptr, i64 16
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%4 = load i32, ptr %iv5, align 8
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%cmp26 = icmp slt i32 %conv.i, 0
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%cmp.i72 = icmp eq i32 %4, 0
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%or.i7480 = or i1 %cmp.i72, %cmp26
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%and3183 = and i1 %or.i5977, %or.i6478
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%and3284 = and i1 %and3183, %or.i6979
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%and3385 = and i1 %and3284, %or.i7480
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%and33 = zext i1 %and3385 to i32
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ret i32 %and33
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}
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