ea7f43ec14
scheduling, is previously vectorized. If the main node was vectorized already, but does not require scheduling, we still can try to vectorize it in this new node instead of gathering.
110 lines
4.2 KiB
LLVM
110 lines
4.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
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; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
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define void @test(double %0) {
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; CHECK-LABEL: define void @test(
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; CHECK-SAME: double [[TMP0:%.*]]) {
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; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[TMP0]], i32 0
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; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <2 x i32> zeroinitializer
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; CHECK-NEXT: br label [[TMP4:%.*]]
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; CHECK: 4:
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; CHECK-NEXT: [[TMP5:%.*]] = fsub <2 x double> zeroinitializer, [[TMP3]]
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; CHECK-NEXT: [[TMP6:%.*]] = fsub <2 x double> zeroinitializer, [[TMP3]]
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; CHECK-NEXT: br label [[DOTBACKEDGE:%.*]]
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; CHECK: .backedge:
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; CHECK-NEXT: [[TMP7:%.*]] = fmul <2 x double> [[TMP5]], [[TMP6]]
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; CHECK-NEXT: [[TMP8:%.*]] = fcmp olt <2 x double> [[TMP7]], zeroinitializer
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; CHECK-NEXT: br label [[TMP4]]
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;
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br label %2
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2:
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%3 = fsub double 0.000000e+00, %0
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%4 = fsub double 0.000000e+00, %0
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%5 = fsub double 0.000000e+00, %0
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br label %.backedge
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.backedge:
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%6 = fmul double %4, %5
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%7 = fcmp olt double %6, 0.000000e+00
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%8 = fmul double %5, %3
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%9 = fcmp olt double %8, 0.000000e+00
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br label %2
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}
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define void @test1(double %0, <4 x double> %v) {
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; CHECK-LABEL: define void @test1(
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; CHECK-SAME: double [[TMP0:%.*]], <4 x double> [[V:%.*]]) {
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; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x double> [[V]], <4 x double> poison, <2 x i32> <i32 poison, i32 0>
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; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> [[TMP2]], double [[TMP0]], i32 0
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; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 0>
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; CHECK-NEXT: br label [[TMP5:%.*]]
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; CHECK: 5:
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; CHECK-NEXT: [[TMP6:%.*]] = fsub <4 x double> <double 1.000000e+00, double 2.000000e+00, double 3.000000e+00, double 4.000000e+00>, [[V]]
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; CHECK-NEXT: [[TMP7:%.*]] = fsub <4 x double> <double 0.000000e+00, double 1.000000e+00, double 0.000000e+00, double 0.000000e+00>, [[TMP4]]
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; CHECK-NEXT: br label [[DOTBACKEDGE:%.*]]
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; CHECK: .backedge:
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; CHECK-NEXT: [[TMP8:%.*]] = fmul <4 x double> [[TMP7]], [[TMP6]]
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; CHECK-NEXT: [[TMP9:%.*]] = fcmp olt <4 x double> [[TMP8]], zeroinitializer
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; CHECK-NEXT: br label [[TMP5]]
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;
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%e0 = extractelement <4 x double> %v, i32 0
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%e1 = extractelement <4 x double> %v, i32 1
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%e2 = extractelement <4 x double> %v, i32 2
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%e3 = extractelement <4 x double> %v, i32 3
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br label %2
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2:
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%m1 = fsub double 1.000000e+00, %e0
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%m2 = fsub double 2.000000e+00, %e1
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%m3 = fsub double 3.000000e+00, %e2
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%m4 = fsub double 4.000000e+00, %e3
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%3 = fsub double 0.000000e+00, %0
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%4 = fsub double 0.000000e+00, %0
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%5 = fsub double 0.000000e+00, %0
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br label %.backedge
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.backedge:
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%6 = fmul double %m1, %m2
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%7 = fcmp olt double %6, 0.000000e+00
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%8 = fmul double %3, %m1
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%9 = fcmp olt double %8, 0.000000e+00
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%10 = fmul double %4, %m3
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%11 = fcmp olt double %10, 0.000000e+00
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%12 = fmul double %5, %m4
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%13 = fcmp olt double %12, 0.000000e+00
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br label %2
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}
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define void @test2(double %0) {
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; CHECK-LABEL: define void @test2(
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; CHECK-SAME: double [[TMP0:%.*]]) {
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; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> poison, double [[TMP0]], i32 0
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; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> poison, <2 x i32> zeroinitializer
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; CHECK-NEXT: br label [[TMP4:%.*]]
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; CHECK: 4:
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; CHECK-NEXT: [[TMP5:%.*]] = fsub <2 x double> <double 3.000000e+00, double 2.000000e+00>, [[TMP3]]
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; CHECK-NEXT: [[TMP6:%.*]] = fsub <2 x double> <double 3.000000e+00, double 1.000000e+00>, [[TMP3]]
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; CHECK-NEXT: br label [[DOTBACKEDGE:%.*]]
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; CHECK: .backedge:
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; CHECK-NEXT: [[TMP7:%.*]] = fmul <2 x double> [[TMP5]], [[TMP6]]
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; CHECK-NEXT: [[TMP8:%.*]] = fcmp olt <2 x double> [[TMP7]], zeroinitializer
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; CHECK-NEXT: br label [[TMP4]]
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;
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br label %2
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2:
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%3 = fsub double 1.000000e+00, %0
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%4 = fsub double 2.000000e+00, %0
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%5 = fsub double 3.000000e+00, %0
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br label %.backedge
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.backedge:
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%6 = fmul double %4, %3
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%7 = fcmp olt double %6, 0.000000e+00
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%8 = fmul double %5, %5
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%9 = fcmp olt double %8, 0.000000e+00
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br label %2
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}
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