93a9be0cea
Previously only the very first gather/buildvector node might be probed for reshuffling of other nodes. But the compiler may do the same for other gather/buildvector nodes too, just need to check the dependency and postpone the emission of the dependent nodes, if the origin nodes were not emitted yet. Part of D110978 Differential Revision: https://reviews.llvm.org/D144958
46 lines
1.6 KiB
LLVM
46 lines
1.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -passes=slp-vectorizer < %s | FileCheck %s
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define i64 @test() {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: bb1:
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; CHECK-NEXT: br label [[BB3:%.*]]
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; CHECK: bb2:
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; CHECK-NEXT: br label [[BB3]]
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; CHECK: bb3:
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; CHECK-NEXT: [[TMP:%.*]] = phi i32 [ 0, [[BB2:%.*]] ], [ 0, [[BB1:%.*]] ]
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; CHECK-NEXT: [[TMP4:%.*]] = phi i32 [ 0, [[BB2]] ], [ 0, [[BB1]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i32> poison, i32 [[TMP4]], i32 0
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; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[TMP0]], <8 x i32> poison, <8 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> [[TMP1]])
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; CHECK-NEXT: [[OP_RDX:%.*]] = mul i32 [[TMP2]], [[TMP4]]
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; CHECK-NEXT: [[OP_RDX1:%.*]] = mul i32 [[TMP4]], [[TMP4]]
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; CHECK-NEXT: [[OP_RDX2:%.*]] = mul i32 [[OP_RDX]], [[OP_RDX1]]
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; CHECK-NEXT: [[OP_RDX3:%.*]] = mul i32 [[OP_RDX2]], [[TMP]]
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; CHECK-NEXT: [[TMP65:%.*]] = sext i32 [[OP_RDX3]] to i64
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; CHECK-NEXT: ret i64 [[TMP65]]
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;
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bb1:
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br label %bb3
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bb2:
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br label %bb3
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bb3:
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%tmp = phi i32 [ 0, %bb2 ], [ 0, %bb1 ]
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%tmp4 = phi i32 [ 0, %bb2 ], [ 0, %bb1 ]
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%tmp5 = mul i32 %tmp, %tmp4
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%tmp6 = mul i32 %tmp5, %tmp4
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%tmp7 = mul i32 %tmp6, %tmp4
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%tmp8 = mul i32 %tmp7, %tmp4
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%tmp9 = mul i32 %tmp8, %tmp4
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%tmp10 = mul i32 %tmp9, %tmp4
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%tmp11 = mul i32 %tmp10, %tmp4
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%tmp12 = mul i32 %tmp11, %tmp4
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%tmp13 = mul i32 %tmp12, %tmp4
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%tmp14 = mul i32 %tmp13, %tmp4
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%tmp15 = mul i32 %tmp14, %tmp4
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%tmp65 = sext i32 %tmp15 to i64
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ret i64 %tmp65
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}
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