31eaf86a1e
This improves overall analysis for minbitwidth in SLP. It allows to
analyze the trees with store/insertelement root nodes. Also, instead of
using single minbitwidth, detected from the very first analysis stage,
it tries to detect the best one for each trunc/ext subtree in the graph
and use it for the subtree.
Results in better code and less vector register pressure.
Metric: size..text
Program size..text
results results0 diff
test-suite :: SingleSource/Benchmarks/Adobe-C++/simple_types_loop_invariant.test 92549.00 92609.00 0.1%
test-suite :: External/SPEC/CINT2017speed/625.x264_s/625.x264_s.test 663381.00 663493.00 0.0%
test-suite :: External/SPEC/CINT2017rate/525.x264_r/525.x264_r.test 663381.00 663493.00 0.0%
test-suite :: MultiSource/Benchmarks/Bullet/bullet.test 307182.00 307214.00 0.0%
test-suite :: External/SPEC/CFP2017speed/638.imagick_s/638.imagick_s.test 1394420.00 1394484.00 0.0%
test-suite :: External/SPEC/CFP2017rate/538.imagick_r/538.imagick_r.test 1394420.00 1394484.00 0.0%
test-suite :: External/SPEC/CFP2017rate/510.parest_r/510.parest_r.test 2040257.00 2040273.00 0.0%
test-suite :: External/SPEC/CFP2017rate/526.blender_r/526.blender_r.test 12396098.00 12395858.00 -0.0%
test-suite :: External/SPEC/CINT2006/445.gobmk/445.gobmk.test 909944.00 909768.00 -0.0%
SingleSource/Benchmarks/Adobe-C++/simple_types_loop_invariant - 4 scalar
instructions remain scalar (good).
Spec2017/x264 - the whole function idct4x4dc is vectorized using <16
x i16> instead of <16 x i32>, also zext/trunc are removed. In other
places last vector zext/sext removed and replaced by
extractelement + scalar zext/sext pair.
MultiSource/Benchmarks/Bullet/bullet - reduce or <4 x i32> replaced by
reduce or <4 x i8>
Spec2017/imagick - Removed extra zext from 2 packs of the operations.
Spec2017/parest - Removed extra zext, replaced by extractelement+scalar
zext
Spec2017/blender - the whole bunch of vector zext/sext replaced by
extractelement+scalar zext/sext, some extra code vectorized in smaller
types.
Spec2006/gobmk - fixed cost estimation, some small code remains scalar.
Original Pull Request: https://github.com/llvm/llvm-project/pull/84334
The patch has the same functionality (no test changes, no changes in
benchmarks) as the original patch, just has some compile time
improvements + fixes for xxhash unittest, discovered earlier in the
previous version of the patch.
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/84536
77 lines
2.3 KiB
LLVM
77 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt -S --passes=slp-vectorizer -slp-threshold=-99999 -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
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define void @test(i32 %arg) {
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; CHECK-LABEL: define void @test(
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; CHECK-SAME: i32 [[ARG:%.*]]) {
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; CHECK-NEXT: bb:
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; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[ARG]], i32 0
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; CHECK-NEXT: br label [[BB2:%.*]]
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; CHECK: bb2:
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; CHECK-NEXT: switch i32 0, label [[BB10:%.*]] [
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; CHECK-NEXT: i32 0, label [[BB9:%.*]]
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; CHECK-NEXT: i32 11, label [[BB9]]
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; CHECK-NEXT: i32 1, label [[BB4:%.*]]
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; CHECK-NEXT: ]
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; CHECK: bb3:
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; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[TMP0]], i32 0
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; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
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; CHECK-NEXT: switch i32 0, label [[BB10]] [
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; CHECK-NEXT: i32 18, label [[BB7:%.*]]
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; CHECK-NEXT: i32 1, label [[BB7]]
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; CHECK-NEXT: i32 0, label [[BB10]]
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; CHECK-NEXT: ]
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; CHECK: bb4:
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; CHECK-NEXT: [[TMP3:%.*]] = phi <2 x i32> [ [[TMP0]], [[BB2]] ]
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; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[TMP3]], i32 0
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; CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
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; CHECK-NEXT: [[GETELEMENTPTR:%.*]] = getelementptr i32, ptr null, i64 [[TMP5]]
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; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i32> [[TMP3]], i32 1
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; CHECK-NEXT: [[TMP6:%.*]] = zext i32 [[TMP7]] to i64
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; CHECK-NEXT: [[GETELEMENTPTR6:%.*]] = getelementptr i32, ptr null, i64 [[TMP6]]
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; CHECK-NEXT: ret void
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; CHECK: bb7:
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; CHECK-NEXT: [[PHI8:%.*]] = phi i64 [ [[TMP2]], [[BB3:%.*]] ], [ [[TMP2]], [[BB3]] ]
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; CHECK-NEXT: br label [[BB9]]
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; CHECK: bb9:
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; CHECK-NEXT: ret void
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; CHECK: bb10:
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; CHECK-NEXT: ret void
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;
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bb:
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%zext = zext i32 %arg to i64
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%zext1 = zext i32 0 to i64
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br label %bb2
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bb2:
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switch i32 0, label %bb10 [
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i32 0, label %bb9
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i32 11, label %bb9
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i32 1, label %bb4
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]
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bb3:
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switch i32 0, label %bb10 [
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i32 18, label %bb7
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i32 1, label %bb7
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i32 0, label %bb10
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]
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bb4:
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%phi = phi i64 [ %zext, %bb2 ]
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%phi5 = phi i64 [ %zext1, %bb2 ]
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%getelementptr = getelementptr i32, ptr null, i64 %phi
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%getelementptr6 = getelementptr i32, ptr null, i64 %phi5
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ret void
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bb7:
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%phi8 = phi i64 [ %zext, %bb3 ], [ %zext, %bb3 ]
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br label %bb9
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bb9:
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ret void
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bb10:
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ret void
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}
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