eecb99c5f6
These tests rely on SCEV looking recognizing an "or" with no common bits as an "add". Add the disjoint flag to relevant or instructions in preparation for switching SCEV to use the flag instead of the ValueTracking query. The IR with disjoint flag matches what InstCombine would produce.
36 lines
1.7 KiB
LLVM
36 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 < %s | FileCheck %s
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define dso_local void @rftbsub(ptr %a) local_unnamed_addr #0 {
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; CHECK-LABEL: @rftbsub(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, ptr [[A:%.*]], i64 2
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; CHECK-NEXT: [[SUB22:%.*]] = fsub double undef, undef
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; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[ARRAYIDX6]], align 8
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; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x double> [[TMP1]], i32 1
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; CHECK-NEXT: [[ADD16:%.*]] = fadd double [[TMP2]], undef
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; CHECK-NEXT: [[MUL18:%.*]] = fmul double undef, [[ADD16]]
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; CHECK-NEXT: [[ADD19:%.*]] = fadd double undef, [[MUL18]]
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; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[ADD19]], i32 0
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; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP3]], double [[SUB22]], i32 1
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; CHECK-NEXT: [[TMP5:%.*]] = fsub <2 x double> [[TMP1]], [[TMP4]]
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; CHECK-NEXT: store <2 x double> [[TMP5]], ptr [[ARRAYIDX6]], align 8
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; CHECK-NEXT: unreachable
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;
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entry:
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%arrayidx6 = getelementptr inbounds double, ptr %a, i64 2
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%0 = load double, ptr %arrayidx6, align 8
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%1 = or disjoint i64 2, 1
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%arrayidx12 = getelementptr inbounds double, ptr %a, i64 %1
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%2 = load double, ptr %arrayidx12, align 8
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%add16 = fadd double %2, undef
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%mul18 = fmul double undef, %add16
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%add19 = fadd double undef, %mul18
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%sub22 = fsub double undef, undef
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%sub25 = fsub double %0, %add19
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store double %sub25, ptr %arrayidx6, align 8
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%sub29 = fsub double %2, %sub22
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store double %sub29, ptr %arrayidx12, align 8
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unreachable
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}
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