cea5d2870f
Similar to D125411, but for ARM64X. ARM64X PE binaries are hybrids containing both ARM64EC and pure ARM64 variants in one file. They are usually linked by passing separate ARM64EC and ARM64 object files to linker. Linked binaries use ARM64 machine and contain additional CHPE metadata in their load config. CHPE metadata support is not part of this patch, I plan to send that later. Using ARM64X as a machine type of object files themselves is somewhat ambiguous, but such files are allowed by MSVC. It treats them as ARM64 or ARM64EC object, depending on the context. Such objects can be produced with cvtres.exe -machine:arm64x. Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D148517
105 lines
4.8 KiB
Plaintext
105 lines
4.8 KiB
Plaintext
// Check that cvtres properly generates COFF for different machine types. The
|
|
// only things that changes with machine type are the machine constant listed
|
|
// in the COFF header, and the relocation types in the relocation tables.
|
|
// The input was generated with the following command, using the original Windows
|
|
// rc.exe:
|
|
// > rc /fo test_resource.res /nologo test_resource.rc
|
|
// The object files we are comparing against were generated with these commands
|
|
// using the original Windows cvtres.exe.
|
|
// > cvtres /machine:X86 /readonly /nologo /out:test_resource.obj.coff \
|
|
// test_resource.res
|
|
// > cvtres /machine:X64 /readonly /nologo /out:test_resource.obj.coff.x64 \
|
|
// test_resource.res
|
|
// > cvtres /machine:ARM /readonly /nologo /out:test_resource.obj.coff.x64 \
|
|
// test_resource.res
|
|
|
|
RUN: llvm-cvtres /machine:X86 /out:%t %p/Inputs/test_resource.res
|
|
RUN: llvm-readobj -h -r %t | FileCheck %s -check-prefix=X86
|
|
|
|
RUN: llvm-cvtres /machine:X64 /out:%t %p/Inputs/test_resource.res
|
|
RUN: llvm-readobj -h -r %t | FileCheck %s -check-prefix=X64
|
|
|
|
RUN: llvm-cvtres /machine:ARM /out:%t %p/Inputs/test_resource.res
|
|
RUN: llvm-readobj -h -r %t | FileCheck %s -check-prefix=ARM
|
|
|
|
RUN: llvm-cvtres /machine:ARM64 /out:%t %p/Inputs/test_resource.res
|
|
RUN: llvm-readobj -h -r %t | FileCheck %s -check-prefix=ARM64
|
|
|
|
RUN: llvm-cvtres /machine:ARM64EC /out:%t %p/Inputs/test_resource.res
|
|
RUN: llvm-readobj -h -r %t | FileCheck %s -check-prefix=ARM64EC
|
|
|
|
RUN: llvm-cvtres /machine:ARM64X /out:%t %p/Inputs/test_resource.res
|
|
RUN: llvm-readobj -h -r %t | FileCheck %s -check-prefix=ARM64X
|
|
|
|
X86: Machine: IMAGE_FILE_MACHINE_I386 (0x14C)
|
|
X86-DAG: Relocations [
|
|
X86-DAG: .rsrc$01 {
|
|
X86-NEXT: 0x1E8 IMAGE_REL_I386_DIR32NB $R000000
|
|
X86-NEXT: 0x198 IMAGE_REL_I386_DIR32NB $R000001
|
|
X86-NEXT: 0x1A8 IMAGE_REL_I386_DIR32NB $R000002
|
|
X86-NEXT: 0x1C8 IMAGE_REL_I386_DIR32NB $R000003
|
|
X86-NEXT: 0x1D8 IMAGE_REL_I386_DIR32NB $R000004
|
|
X86-NEXT: 0x1F8 IMAGE_REL_I386_DIR32NB $R000005
|
|
X86-NEXT: 0x1B8 IMAGE_REL_I386_DIR32NB $R000006
|
|
X86-NEXT: 0x188 IMAGE_REL_I386_DIR32NB $R000007
|
|
|
|
X64: Machine: IMAGE_FILE_MACHINE_AMD64 (0x8664)
|
|
X64-DAG: Relocations [
|
|
X64-DAG: .rsrc$01 {
|
|
X64-NEXT: 0x1E8 IMAGE_REL_AMD64_ADDR32NB $R000000
|
|
X64-NEXT: 0x198 IMAGE_REL_AMD64_ADDR32NB $R000001
|
|
X64-NEXT: 0x1A8 IMAGE_REL_AMD64_ADDR32NB $R000002
|
|
X64-NEXT: 0x1C8 IMAGE_REL_AMD64_ADDR32NB $R000003
|
|
X64-NEXT: 0x1D8 IMAGE_REL_AMD64_ADDR32NB $R000004
|
|
X64-NEXT: 0x1F8 IMAGE_REL_AMD64_ADDR32NB $R000005
|
|
X64-NEXT: 0x1B8 IMAGE_REL_AMD64_ADDR32NB $R000006
|
|
X64-NEXT: 0x188 IMAGE_REL_AMD64_ADDR32NB $R000007
|
|
|
|
ARM: Machine: IMAGE_FILE_MACHINE_ARMNT (0x1C4)
|
|
ARM-DAG: Relocations [
|
|
ARM-DAG: .rsrc$01 {
|
|
ARM-NEXT: 0x1E8 IMAGE_REL_ARM_ADDR32NB $R000000
|
|
ARM-NEXT: 0x198 IMAGE_REL_ARM_ADDR32NB $R000001
|
|
ARM-NEXT: 0x1A8 IMAGE_REL_ARM_ADDR32NB $R000002
|
|
ARM-NEXT: 0x1C8 IMAGE_REL_ARM_ADDR32NB $R000003
|
|
ARM-NEXT: 0x1D8 IMAGE_REL_ARM_ADDR32NB $R000004
|
|
ARM-NEXT: 0x1F8 IMAGE_REL_ARM_ADDR32NB $R000005
|
|
ARM-NEXT: 0x1B8 IMAGE_REL_ARM_ADDR32NB $R000006
|
|
ARM-NEXT: 0x188 IMAGE_REL_ARM_ADDR32NB $R000007
|
|
|
|
ARM64: Machine: IMAGE_FILE_MACHINE_ARM64 (0xAA64)
|
|
ARM64-DAG: Relocations [
|
|
ARM64-DAG: .rsrc$01 {
|
|
ARM64-NEXT: 0x1E8 IMAGE_REL_ARM64_ADDR32NB $R000000
|
|
ARM64-NEXT: 0x198 IMAGE_REL_ARM64_ADDR32NB $R000001
|
|
ARM64-NEXT: 0x1A8 IMAGE_REL_ARM64_ADDR32NB $R000002
|
|
ARM64-NEXT: 0x1C8 IMAGE_REL_ARM64_ADDR32NB $R000003
|
|
ARM64-NEXT: 0x1D8 IMAGE_REL_ARM64_ADDR32NB $R000004
|
|
ARM64-NEXT: 0x1F8 IMAGE_REL_ARM64_ADDR32NB $R000005
|
|
ARM64-NEXT: 0x1B8 IMAGE_REL_ARM64_ADDR32NB $R000006
|
|
ARM64-NEXT: 0x188 IMAGE_REL_ARM64_ADDR32NB $R000007
|
|
|
|
ARM64EC: Machine: IMAGE_FILE_MACHINE_ARM64EC (0xA641)
|
|
ARM64EC-DAG: Relocations [
|
|
ARM64EC-DAG: .rsrc$01 {
|
|
ARM64EC-NEXT: 0x1E8 IMAGE_REL_ARM64_ADDR32NB $R000000
|
|
ARM64EC-NEXT: 0x198 IMAGE_REL_ARM64_ADDR32NB $R000001
|
|
ARM64EC-NEXT: 0x1A8 IMAGE_REL_ARM64_ADDR32NB $R000002
|
|
ARM64EC-NEXT: 0x1C8 IMAGE_REL_ARM64_ADDR32NB $R000003
|
|
ARM64EC-NEXT: 0x1D8 IMAGE_REL_ARM64_ADDR32NB $R000004
|
|
ARM64EC-NEXT: 0x1F8 IMAGE_REL_ARM64_ADDR32NB $R000005
|
|
ARM64EC-NEXT: 0x1B8 IMAGE_REL_ARM64_ADDR32NB $R000006
|
|
ARM64EC-NEXT: 0x188 IMAGE_REL_ARM64_ADDR32NB $R000007
|
|
|
|
ARM64X: Machine: IMAGE_FILE_MACHINE_ARM64X (0xA64E)
|
|
ARM64X-DAG: Relocations [
|
|
ARM64X-DAG: .rsrc$01 {
|
|
ARM64X-NEXT: 0x1E8 IMAGE_REL_ARM64_ADDR32NB $R000000
|
|
ARM64X-NEXT: 0x198 IMAGE_REL_ARM64_ADDR32NB $R000001
|
|
ARM64X-NEXT: 0x1A8 IMAGE_REL_ARM64_ADDR32NB $R000002
|
|
ARM64X-NEXT: 0x1C8 IMAGE_REL_ARM64_ADDR32NB $R000003
|
|
ARM64X-NEXT: 0x1D8 IMAGE_REL_ARM64_ADDR32NB $R000004
|
|
ARM64X-NEXT: 0x1F8 IMAGE_REL_ARM64_ADDR32NB $R000005
|
|
ARM64X-NEXT: 0x1B8 IMAGE_REL_ARM64_ADDR32NB $R000006
|
|
ARM64X-NEXT: 0x188 IMAGE_REL_ARM64_ADDR32NB $R000007
|