dc90af501f
New versions I2.1, F2.2, D2.2 A2.1 Make F and Zfinx imply Zicsr. Make G imply Zifencei. This should have no impact to generated code. We have no plans to require Zicsr/Zifencei extension to be explicitly enabled to use Zicsr/Zifencei instructions in assembly. See https://reviews.llvm.org/D147183 for documentation regarding what version specification we implement. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D147179
45 lines
1.4 KiB
ArmAsm
45 lines
1.4 KiB
ArmAsm
## Test llvm-readobj & llvm-readelf can decode RISC-V attributes correctly.
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# RUN: llvm-mc -triple riscv32 -filetype obj -o %t.rv32.o %s
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# RUN: llvm-mc -triple riscv64 -filetype obj -o %t.rv64.o %s
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# RUN: llvm-readobj --arch-specific %t.rv32.o \
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# RUN: | FileCheck %s --check-prefix=CHECK-OBJ
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# RUN: llvm-readelf -A %t.rv32.o \
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# RUN: | FileCheck %s --check-prefix=CHECK-OBJ
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# RUN: llvm-readobj --arch-specific %t.rv64.o \
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# RUN: | FileCheck %s --check-prefix=CHECK-OBJ
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# RUN: llvm-readelf -A %t.rv64.o \
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# RUN: | FileCheck %s --check-prefix=CHECK-OBJ
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.attribute Tag_stack_align, 16
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# CHECK-OBJ: Tag: 4
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# CHECK-OBJ-NEXT: Value: 16
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# CHECK-OBJ-NEXT: TagName: stack_align
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# CHECK-OBJ-NEXT: Description: Stack alignment is 16-bytes
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.attribute Tag_arch, "rv32i2p1_m2p0_a2p1_c2p0"
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# CHECK-OBJ: Tag: 5
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# CHECK-OBJ-NEXT: TagName: arch
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# CHECK-OBJ-NEXT: Value: rv32i2p1_m2p0_a2p1_c2p0
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.attribute Tag_unaligned_access, 0
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# CHECK-OBJ: Tag: 6
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# CHECK-OBJ-NEXT: Value: 0
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# CHECK-OBJ-NEXT: TagName: unaligned_access
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# CHECK-OBJ-NEXT: Description: No unaligned access
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.attribute Tag_priv_spec, 2
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# CHECK-OBJ: Tag: 8
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# CHECK-OBJ-NEXT: TagName: priv_spec
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# CHECK-OBJ-NEXT: Value: 2
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.attribute Tag_priv_spec_minor, 0
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# CHECK-OBJ: Tag: 10
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# CHECK-OBJ-NEXT: TagName: priv_spec_minor
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# CHECK-OBJ-NEXT: Value: 0
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.attribute Tag_priv_spec_revision, 0
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# CHECK-OBJ: Tag: 12
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# CHECK-OBJ-NEXT: TagName: priv_spec_revision
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# CHECK-OBJ-NEXT: Value: 0
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