36a3f8f647
Adds a second parameter (default to 0) to isLegalAddImmediate, to represent a scalable immediate. Extends the AArch64 implementation to match immediates based on what addvl and inc[h|w|d] support.
107 lines
2.8 KiB
C++
107 lines
2.8 KiB
C++
#include "AArch64Subtarget.h"
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#include "AArch64TargetMachine.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/TargetSelect.h"
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#include "gtest/gtest.h"
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#include <initializer_list>
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#include <memory>
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using namespace llvm;
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namespace {
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struct TestCase {
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int64_t Imm;
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bool Result;
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};
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const std::initializer_list<TestCase> Tests = {
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// ScalableImm, Result
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// No change, easily 'supported'
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{0, true},
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// addvl increments by whole registers, range [-32,31]
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// +(16 * vscale), one register's worth
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{16, true},
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// -(32 * 16 * vscale)
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{-512, true},
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// -(33 * 16 * vscale)
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{-528, false},
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// +(31 * 16 * vscale)
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{496, true},
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// +(32 * 16 * vscale)
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{512, false},
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// inc[h|w|d] increments by the number of 16/32/64bit elements in a
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// register. mult_imm is in the range [1,16]
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// +(mult_imm * num_elts * vscale)
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// +(1 * 8 * vscale), 16 bit
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{8, true},
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// +(15 * 8 * vscale), 16 bit
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{120, true},
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// +(1 * 4 * vscale), 32 bit
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{4, true},
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// +(7 * 4 * vscale), 32 bit
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{28, true},
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// +(1 * 2 * vscale), 64 bit
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{2, true},
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// +(13 * 2 * vscale), 64 bit
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{26, true},
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// +(17 * 8 * vscale), 16 bit, out of range.
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{136, false},
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// +(19 * 2 * vscale), 64 bit, out of range.
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{38, false},
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// +(21 * 4 * vscale), 32 bit, out of range.
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{84, false},
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// dec[h|w|d] -- Same as above, but negative.
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// -(mult_imm * num_elts * vscale)
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// -(1 * 8 * vscale), 16 bit
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{-8, true},
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// -(15 * 8 * vscale), 16 bit
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{-120, true},
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// -(1 * 4 * vscale), 32 bit
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{-4, true},
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// -(7 * 4 * vscale), 32 bit
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{-28, true},
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// -(1 * 2 * vscale), 64 bit
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{-2, true},
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// -(13 * 2 * vscale), 64 bit
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{-26, true},
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// -(17 * 8 * vscale), 16 bit, out of range.
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{-136, false},
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// -(19 * 2 * vscale), 64 bit, out of range.
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{-38, false},
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// -(21 * 4 * vscale), 32 bit, out of range.
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{-84, false},
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// Invalid; not divisible by the above powers of 2.
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{5, false},
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};
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} // namespace
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TEST(Immediates, Immediates) {
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LLVMInitializeAArch64TargetInfo();
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LLVMInitializeAArch64Target();
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LLVMInitializeAArch64TargetMC();
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std::string Error;
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auto TT = Triple::normalize("aarch64");
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const Target *T = TargetRegistry::lookupTarget(TT, Error);
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std::unique_ptr<TargetMachine> TM(T->createTargetMachine(
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TT, "generic", "+sve2", TargetOptions(), std::nullopt, std::nullopt,
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CodeGenOptLevel::Default));
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AArch64Subtarget ST(TM->getTargetTriple(), TM->getTargetCPU(),
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TM->getTargetCPU(), TM->getTargetFeatureString(), *TM,
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true);
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auto *TLI = ST.getTargetLowering();
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for (const auto &Test : Tests) {
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ASSERT_EQ(TLI->isLegalAddScalableImmediate(Test.Imm), Test.Result);
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}
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}
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