44be5a7fdc
This is another part of #70452 which makes getMemOperandsWithOffsetWidth use a LocationSize for Width, as opposed to the unsigned it currently uses. The advantages on it's own are not super high if getMemOperandsWithOffsetWidth usually uses known sizes, but if the values can come from an MMO it can help be more accurate in case they are Unknown (and in the future, scalable).
322 lines
12 KiB
C++
322 lines
12 KiB
C++
//===- RISCVInstrInfoTest.cpp - RISCVInstrInfo unit tests -----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVInstrInfo.h"
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#include "RISCVSubtarget.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/IR/DebugInfoMetadata.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/TargetSelect.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "gtest/gtest.h"
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#include <memory>
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using namespace llvm;
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namespace {
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class RISCVInstrInfoTest : public testing::TestWithParam<const char *> {
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protected:
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std::unique_ptr<RISCVTargetMachine> TM;
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std::unique_ptr<LLVMContext> Ctx;
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std::unique_ptr<RISCVSubtarget> ST;
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std::unique_ptr<MachineModuleInfo> MMI;
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std::unique_ptr<MachineFunction> MF;
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std::unique_ptr<Module> M;
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static void SetUpTestSuite() {
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LLVMInitializeRISCVTargetInfo();
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LLVMInitializeRISCVTarget();
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LLVMInitializeRISCVTargetMC();
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}
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RISCVInstrInfoTest() {
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std::string Error;
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auto TT(Triple::normalize(GetParam()));
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const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error);
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TargetOptions Options;
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TM.reset(static_cast<RISCVTargetMachine *>(TheTarget->createTargetMachine(
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TT, "generic", "", Options, std::nullopt, std::nullopt,
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CodeGenOptLevel::Default)));
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Ctx = std::make_unique<LLVMContext>();
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M = std::make_unique<Module>("Module", *Ctx);
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M->setDataLayout(TM->createDataLayout());
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auto *FType = FunctionType::get(Type::getVoidTy(*Ctx), false);
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auto *F = Function::Create(FType, GlobalValue::ExternalLinkage, "Test", *M);
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MMI = std::make_unique<MachineModuleInfo>(TM.get());
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ST = std::make_unique<RISCVSubtarget>(
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TM->getTargetTriple(), TM->getTargetCPU(), TM->getTargetCPU(),
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TM->getTargetFeatureString(),
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TM->getTargetTriple().isArch64Bit() ? "lp64" : "ilp32", 0, 0, *TM);
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MF = std::make_unique<MachineFunction>(*F, *TM, *ST, 42, *MMI);
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}
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};
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TEST_P(RISCVInstrInfoTest, IsAddImmediate) {
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const RISCVInstrInfo *TII = ST->getInstrInfo();
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DebugLoc DL;
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MachineInstr *MI1 = BuildMI(*MF, DL, TII->get(RISCV::ADDI), RISCV::X1)
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.addReg(RISCV::X2)
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.addImm(-128)
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.getInstr();
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auto MI1Res = TII->isAddImmediate(*MI1, RISCV::X1);
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ASSERT_TRUE(MI1Res.has_value());
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EXPECT_EQ(MI1Res->Reg, RISCV::X2);
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EXPECT_EQ(MI1Res->Imm, -128);
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EXPECT_FALSE(TII->isAddImmediate(*MI1, RISCV::X2).has_value());
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MachineInstr *MI2 =
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BuildMI(*MF, DL, TII->get(RISCV::LUI), RISCV::X1).addImm(-128).getInstr();
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EXPECT_FALSE(TII->isAddImmediate(*MI2, RISCV::X1));
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// Check ADDIW isn't treated as isAddImmediate.
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if (ST->is64Bit()) {
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MachineInstr *MI3 = BuildMI(*MF, DL, TII->get(RISCV::ADDIW), RISCV::X1)
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.addReg(RISCV::X2)
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.addImm(-128)
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.getInstr();
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EXPECT_FALSE(TII->isAddImmediate(*MI3, RISCV::X1));
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}
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}
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TEST_P(RISCVInstrInfoTest, IsCopyInstrImpl) {
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const RISCVInstrInfo *TII = ST->getInstrInfo();
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DebugLoc DL;
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// ADDI.
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MachineInstr *MI1 = BuildMI(*MF, DL, TII->get(RISCV::ADDI), RISCV::X1)
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.addReg(RISCV::X2)
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.addImm(-128)
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.getInstr();
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auto MI1Res = TII->isCopyInstrImpl(*MI1);
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EXPECT_FALSE(MI1Res.has_value());
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MachineInstr *MI2 = BuildMI(*MF, DL, TII->get(RISCV::ADDI), RISCV::X1)
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.addReg(RISCV::X2)
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.addImm(0)
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.getInstr();
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auto MI2Res = TII->isCopyInstrImpl(*MI2);
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ASSERT_TRUE(MI2Res.has_value());
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EXPECT_EQ(MI2Res->Destination->getReg(), RISCV::X1);
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EXPECT_EQ(MI2Res->Source->getReg(), RISCV::X2);
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// Partial coverage of FSGNJ_* instructions.
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MachineInstr *MI3 = BuildMI(*MF, DL, TII->get(RISCV::FSGNJ_D), RISCV::F1_D)
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.addReg(RISCV::F2_D)
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.addReg(RISCV::F1_D)
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.getInstr();
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auto MI3Res = TII->isCopyInstrImpl(*MI3);
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EXPECT_FALSE(MI3Res.has_value());
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MachineInstr *MI4 = BuildMI(*MF, DL, TII->get(RISCV::FSGNJ_D), RISCV::F1_D)
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.addReg(RISCV::F2_D)
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.addReg(RISCV::F2_D)
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.getInstr();
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auto MI4Res = TII->isCopyInstrImpl(*MI4);
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ASSERT_TRUE(MI4Res.has_value());
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EXPECT_EQ(MI4Res->Destination->getReg(), RISCV::F1_D);
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EXPECT_EQ(MI4Res->Source->getReg(), RISCV::F2_D);
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// ADD. TODO: Should return true for add reg, x0 and add x0, reg.
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MachineInstr *MI5 = BuildMI(*MF, DL, TII->get(RISCV::ADD), RISCV::X1)
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.addReg(RISCV::X2)
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.addReg(RISCV::X3)
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.getInstr();
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auto MI5Res = TII->isCopyInstrImpl(*MI5);
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EXPECT_FALSE(MI5Res.has_value());
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MachineInstr *MI6 = BuildMI(*MF, DL, TII->get(RISCV::ADD), RISCV::X1)
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.addReg(RISCV::X0)
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.addReg(RISCV::X2)
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.getInstr();
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auto MI6Res = TII->isCopyInstrImpl(*MI6);
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EXPECT_FALSE(MI6Res.has_value());
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MachineInstr *MI7 = BuildMI(*MF, DL, TII->get(RISCV::ADD), RISCV::X1)
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.addReg(RISCV::X2)
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.addReg(RISCV::X0)
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.getInstr();
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auto MI7Res = TII->isCopyInstrImpl(*MI7);
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EXPECT_FALSE(MI7Res.has_value());
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}
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TEST_P(RISCVInstrInfoTest, GetMemOperandsWithOffsetWidth) {
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const RISCVInstrInfo *TII = ST->getInstrInfo();
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const TargetRegisterInfo *TRI = ST->getRegisterInfo();
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DebugLoc DL;
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SmallVector<const MachineOperand *> BaseOps;
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LocationSize Width = 0;
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int64_t Offset;
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bool OffsetIsScalable;
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auto MMO = MF->getMachineMemOperand(MachinePointerInfo(),
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MachineMemOperand::MOLoad, 1, Align(1));
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MachineInstr *MI = BuildMI(*MF, DL, TII->get(RISCV::LB), RISCV::X1)
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.addReg(RISCV::X2)
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.addImm(-128)
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.addMemOperand(MMO)
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.getInstr();
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bool Res = TII->getMemOperandsWithOffsetWidth(*MI, BaseOps, Offset,
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OffsetIsScalable, Width, TRI);
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ASSERT_TRUE(Res);
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ASSERT_EQ(BaseOps.size(), 1u);
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ASSERT_TRUE(BaseOps.front()->isReg());
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EXPECT_EQ(BaseOps.front()->getReg(), RISCV::X2);
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EXPECT_EQ(Offset, -128);
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EXPECT_FALSE(OffsetIsScalable);
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EXPECT_EQ(Width, 1u);
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BaseOps.clear();
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MMO = MF->getMachineMemOperand(MachinePointerInfo(),
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MachineMemOperand::MOStore, 4, Align(4));
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MI = BuildMI(*MF, DL, TII->get(RISCV::FSW))
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.addReg(RISCV::F3_F)
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.addReg(RISCV::X3)
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.addImm(36)
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.addMemOperand(MMO);
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Res = TII->getMemOperandsWithOffsetWidth(*MI, BaseOps, Offset,
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OffsetIsScalable, Width, TRI);
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ASSERT_TRUE(Res);
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ASSERT_EQ(BaseOps.size(), 1u);
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ASSERT_TRUE(BaseOps.front()->isReg());
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EXPECT_EQ(BaseOps.front()->getReg(), RISCV::X3);
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EXPECT_EQ(Offset, 36);
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EXPECT_FALSE(OffsetIsScalable);
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EXPECT_EQ(Width, 4u);
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BaseOps.clear();
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MMO = MF->getMachineMemOperand(MachinePointerInfo(),
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MachineMemOperand::MOStore, 16, Align(16));
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MI = BuildMI(*MF, DL, TII->get(RISCV::PseudoVLE32_V_M1), RISCV::V8)
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.addReg(RISCV::X3)
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.addMemOperand(MMO);
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Res = TII->getMemOperandsWithOffsetWidth(*MI, BaseOps, Offset,
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OffsetIsScalable, Width, TRI);
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ASSERT_FALSE(Res); // Vector loads/stored are not handled for now.
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BaseOps.clear();
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MI = BuildMI(*MF, DL, TII->get(RISCV::ADDI), RISCV::X4)
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.addReg(RISCV::X5)
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.addImm(16);
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Res = TII->getMemOperandsWithOffsetWidth(*MI, BaseOps, Offset,
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OffsetIsScalable, Width, TRI);
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BaseOps.clear();
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MMO = MF->getMachineMemOperand(MachinePointerInfo(),
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MachineMemOperand::MOStore, 4, Align(4));
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MI = BuildMI(*MF, DL, TII->get(RISCV::SW))
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.addReg(RISCV::X3)
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.addFrameIndex(2)
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.addImm(4)
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.addMemOperand(MMO);
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Res = TII->getMemOperandsWithOffsetWidth(*MI, BaseOps, Offset,
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OffsetIsScalable, Width, TRI);
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ASSERT_TRUE(Res);
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ASSERT_EQ(BaseOps.size(), 1u);
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ASSERT_TRUE(BaseOps.front()->isFI());
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EXPECT_EQ(BaseOps.front()->getIndex(), 2);
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EXPECT_EQ(Offset, 4);
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EXPECT_FALSE(OffsetIsScalable);
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EXPECT_EQ(Width, 4u);
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}
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static void expectDIEPrintResult(const DIExpression *Expr, StringRef Expected) {
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std::string Output;
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raw_string_ostream OS(Output);
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Expr->print(OS);
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OS.flush();
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EXPECT_EQ(OS.str(), Expected);
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}
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TEST_P(RISCVInstrInfoTest, DescribeLoadedValue) {
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const RISCVInstrInfo *TII = ST->getInstrInfo();
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DebugLoc DL;
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MachineBasicBlock *MBB = MF->CreateMachineBasicBlock();
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MF->getProperties().set(MachineFunctionProperties::Property::NoVRegs);
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// Register move.
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auto *MI1 = BuildMI(*MBB, MBB->begin(), DL, TII->get(RISCV::ADDI), RISCV::X1)
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.addReg(RISCV::X2)
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.addImm(0)
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.getInstr();
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EXPECT_FALSE(TII->describeLoadedValue(*MI1, RISCV::X2).has_value());
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std::optional<ParamLoadedValue> MI1Res =
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TII->describeLoadedValue(*MI1, RISCV::X1);
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ASSERT_TRUE(MI1Res.has_value());
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ASSERT_TRUE(MI1Res->first.isReg());
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EXPECT_EQ(MI1Res->first.getReg(), RISCV::X2);
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expectDIEPrintResult(MI1Res->second, "!DIExpression()");
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// Load immediate.
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auto *MI2 = BuildMI(*MBB, MBB->begin(), DL, TII->get(RISCV::ADDI), RISCV::X3)
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.addReg(RISCV::X0)
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.addImm(111)
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.getInstr();
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std::optional<ParamLoadedValue> MI2Res =
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TII->describeLoadedValue(*MI2, RISCV::X3);
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ASSERT_TRUE(MI2Res.has_value());
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ASSERT_TRUE(MI2Res->first.isReg());
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EXPECT_EQ(MI2Res->first.getReg(), RISCV::X0);
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// TODO: Could be a DW_OP_constu if this is recognised as a immediate load
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// rather than just an addi.
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expectDIEPrintResult(MI2Res->second, "!DIExpression(DW_OP_plus_uconst, 111)");
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// Add immediate.
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auto *MI3 = BuildMI(*MBB, MBB->begin(), DL, TII->get(RISCV::ADDI), RISCV::X2)
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.addReg(RISCV::X3)
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.addImm(222)
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.getInstr();
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std::optional<ParamLoadedValue> MI3Res =
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TII->describeLoadedValue(*MI3, RISCV::X2);
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ASSERT_TRUE(MI3Res.has_value());
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ASSERT_TRUE(MI3Res->first.isReg());
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EXPECT_EQ(MI3Res->first.getReg(), RISCV::X3);
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expectDIEPrintResult(MI3Res->second, "!DIExpression(DW_OP_plus_uconst, 222)");
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// Load value from memory.
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// It would be better (more reflective of real-world describeLoadedValue
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// usage) to test using MachinePointerInfo::getFixedStack, but
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// unfortunately it would be overly fiddly to make this work.
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auto MMO = MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(*MF),
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MachineMemOperand::MOLoad, 1, Align(1));
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auto *MI4 = BuildMI(*MBB, MBB->begin(), DL, TII->get(RISCV::LB), RISCV::X1)
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.addReg(RISCV::X2)
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.addImm(-128)
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.addMemOperand(MMO)
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.getInstr();
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std::optional<ParamLoadedValue> MI4Res =
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TII->describeLoadedValue(*MI4, RISCV::X1);
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ASSERT_TRUE(MI4Res.has_value());
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ASSERT_TRUE(MI4Res->first.isReg());
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EXPECT_EQ(MI4Res->first.getReg(), RISCV::X2);
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expectDIEPrintResult(
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MI4Res->second,
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"!DIExpression(DW_OP_constu, 128, DW_OP_minus, DW_OP_deref_size, 1)");
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MF->deleteMachineBasicBlock(MBB);
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}
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} // namespace
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INSTANTIATE_TEST_SUITE_P(RV32And64, RISCVInstrInfoTest,
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testing::Values("riscv32", "riscv64"));
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