fa3d789df1
Refactor of the llvm-tblgen source into: - a "Basic" library, which contains the bare minimum utilities to build `llvm-min-tablegen` - a "Common" library which contains all of the helpers for TableGen backends. Such helpers can be shared by more than one backend, and even unit tested (e.g. CodeExpander is, maybe we can add more over time) Fixes #80647
284 lines
11 KiB
C++
284 lines
11 KiB
C++
//===- CodeGenInstAlias.cpp - CodeGen InstAlias Class Wrapper -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the CodeGenInstAlias class.
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//
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//===----------------------------------------------------------------------===//
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#include "CodeGenInstAlias.h"
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#include "CodeGenInstruction.h"
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#include "CodeGenRegisters.h"
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#include "CodeGenTarget.h"
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#include "llvm/ADT/StringMap.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/Record.h"
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using namespace llvm;
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/// tryAliasOpMatch - This is a helper function for the CodeGenInstAlias
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/// constructor. It checks if an argument in an InstAlias pattern matches
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/// the corresponding operand of the instruction. It returns true on a
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/// successful match, with ResOp set to the result operand to be used.
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bool CodeGenInstAlias::tryAliasOpMatch(DagInit *Result, unsigned AliasOpNo,
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Record *InstOpRec, bool hasSubOps,
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ArrayRef<SMLoc> Loc, CodeGenTarget &T,
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ResultOperand &ResOp) {
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Init *Arg = Result->getArg(AliasOpNo);
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DefInit *ADI = dyn_cast<DefInit>(Arg);
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Record *ResultRecord = ADI ? ADI->getDef() : nullptr;
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if (ADI && ADI->getDef() == InstOpRec) {
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// If the operand is a record, it must have a name, and the record type
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// must match up with the instruction's argument type.
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if (!Result->getArgName(AliasOpNo))
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PrintFatalError(Loc, "result argument #" + Twine(AliasOpNo) +
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" must have a name!");
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ResOp = ResultOperand(std::string(Result->getArgNameStr(AliasOpNo)),
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ResultRecord);
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return true;
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}
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// For register operands, the source register class can be a subclass
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// of the instruction register class, not just an exact match.
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if (InstOpRec->isSubClassOf("RegisterOperand"))
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InstOpRec = InstOpRec->getValueAsDef("RegClass");
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if (ADI && ADI->getDef()->isSubClassOf("RegisterOperand"))
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ADI = ADI->getDef()->getValueAsDef("RegClass")->getDefInit();
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if (ADI && ADI->getDef()->isSubClassOf("RegisterClass")) {
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if (!InstOpRec->isSubClassOf("RegisterClass"))
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return false;
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if (!T.getRegisterClass(InstOpRec).hasSubClass(
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&T.getRegisterClass(ADI->getDef())))
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return false;
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ResOp = ResultOperand(std::string(Result->getArgNameStr(AliasOpNo)),
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ResultRecord);
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return true;
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}
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// Handle explicit registers.
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if (ADI && ADI->getDef()->isSubClassOf("Register")) {
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if (InstOpRec->isSubClassOf("OptionalDefOperand")) {
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DagInit *DI = InstOpRec->getValueAsDag("MIOperandInfo");
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// The operand info should only have a single (register) entry. We
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// want the register class of it.
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InstOpRec = cast<DefInit>(DI->getArg(0))->getDef();
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}
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if (!InstOpRec->isSubClassOf("RegisterClass"))
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return false;
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if (!T.getRegisterClass(InstOpRec).contains(
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T.getRegBank().getReg(ADI->getDef())))
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PrintFatalError(Loc, "fixed register " + ADI->getDef()->getName() +
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" is not a member of the " +
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InstOpRec->getName() + " register class!");
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if (Result->getArgName(AliasOpNo))
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PrintFatalError(Loc, "result fixed register argument must "
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"not have a name!");
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ResOp = ResultOperand(ResultRecord);
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return true;
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}
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// Handle "zero_reg" for optional def operands.
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if (ADI && ADI->getDef()->getName() == "zero_reg") {
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// Check if this is an optional def.
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// Tied operands where the source is a sub-operand of a complex operand
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// need to represent both operands in the alias destination instruction.
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// Allow zero_reg for the tied portion. This can and should go away once
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// the MC representation of things doesn't use tied operands at all.
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// if (!InstOpRec->isSubClassOf("OptionalDefOperand"))
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// throw TGError(Loc, "reg0 used for result that is not an "
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// "OptionalDefOperand!");
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ResOp = ResultOperand(static_cast<Record *>(nullptr));
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return true;
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}
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// Literal integers.
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if (IntInit *II = dyn_cast<IntInit>(Arg)) {
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if (hasSubOps || !InstOpRec->isSubClassOf("Operand"))
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return false;
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// Integer arguments can't have names.
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if (Result->getArgName(AliasOpNo))
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PrintFatalError(Loc, "result argument #" + Twine(AliasOpNo) +
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" must not have a name!");
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ResOp = ResultOperand(II->getValue());
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return true;
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}
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// Bits<n> (also used for 0bxx literals)
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if (BitsInit *BI = dyn_cast<BitsInit>(Arg)) {
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if (hasSubOps || !InstOpRec->isSubClassOf("Operand"))
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return false;
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if (!BI->isComplete())
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return false;
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// Convert the bits init to an integer and use that for the result.
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IntInit *II = dyn_cast_or_null<IntInit>(
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BI->convertInitializerTo(IntRecTy::get(BI->getRecordKeeper())));
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if (!II)
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return false;
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ResOp = ResultOperand(II->getValue());
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return true;
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}
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// If both are Operands with the same MVT, allow the conversion. It's
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// up to the user to make sure the values are appropriate, just like
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// for isel Pat's.
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if (InstOpRec->isSubClassOf("Operand") && ADI &&
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ADI->getDef()->isSubClassOf("Operand")) {
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// FIXME: What other attributes should we check here? Identical
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// MIOperandInfo perhaps?
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if (InstOpRec->getValueInit("Type") != ADI->getDef()->getValueInit("Type"))
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return false;
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ResOp = ResultOperand(std::string(Result->getArgNameStr(AliasOpNo)),
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ADI->getDef());
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return true;
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}
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return false;
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}
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unsigned CodeGenInstAlias::ResultOperand::getMINumOperands() const {
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if (!isRecord())
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return 1;
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Record *Rec = getRecord();
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if (!Rec->isSubClassOf("Operand"))
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return 1;
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DagInit *MIOpInfo = Rec->getValueAsDag("MIOperandInfo");
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if (MIOpInfo->getNumArgs() == 0) {
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// Unspecified, so it defaults to 1
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return 1;
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}
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return MIOpInfo->getNumArgs();
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}
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CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) : TheDef(R) {
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Result = R->getValueAsDag("ResultInst");
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AsmString = std::string(R->getValueAsString("AsmString"));
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// Verify that the root of the result is an instruction.
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DefInit *DI = dyn_cast<DefInit>(Result->getOperator());
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if (!DI || !DI->getDef()->isSubClassOf("Instruction"))
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PrintFatalError(R->getLoc(),
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"result of inst alias should be an instruction");
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ResultInst = &T.getInstruction(DI->getDef());
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// NameClass - If argument names are repeated, we need to verify they have
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// the same class.
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StringMap<Record *> NameClass;
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for (unsigned i = 0, e = Result->getNumArgs(); i != e; ++i) {
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DefInit *ADI = dyn_cast<DefInit>(Result->getArg(i));
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if (!ADI || !Result->getArgName(i))
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continue;
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// Verify we don't have something like: (someinst GR16:$foo, GR32:$foo)
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// $foo can exist multiple times in the result list, but it must have the
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// same type.
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Record *&Entry = NameClass[Result->getArgNameStr(i)];
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if (Entry && Entry != ADI->getDef())
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PrintFatalError(R->getLoc(), "result value $" + Result->getArgNameStr(i) +
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" is both " + Entry->getName() +
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" and " + ADI->getDef()->getName() +
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"!");
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Entry = ADI->getDef();
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}
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// Decode and validate the arguments of the result.
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unsigned AliasOpNo = 0;
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for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
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// Tied registers don't have an entry in the result dag unless they're part
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// of a complex operand, in which case we include them anyways, as we
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// don't have any other way to specify the whole operand.
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if (ResultInst->Operands[i].MINumOperands == 1 &&
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ResultInst->Operands[i].getTiedRegister() != -1) {
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// Tied operands of different RegisterClass should be explicit within an
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// instruction's syntax and so cannot be skipped.
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int TiedOpNum = ResultInst->Operands[i].getTiedRegister();
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if (ResultInst->Operands[i].Rec->getName() ==
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ResultInst->Operands[TiedOpNum].Rec->getName())
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continue;
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}
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if (AliasOpNo >= Result->getNumArgs())
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PrintFatalError(R->getLoc(), "not enough arguments for instruction!");
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Record *InstOpRec = ResultInst->Operands[i].Rec;
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unsigned NumSubOps = ResultInst->Operands[i].MINumOperands;
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ResultOperand ResOp(static_cast<int64_t>(0));
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if (tryAliasOpMatch(Result, AliasOpNo, InstOpRec, (NumSubOps > 1),
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R->getLoc(), T, ResOp)) {
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// If this is a simple operand, or a complex operand with a custom match
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// class, then we can match is verbatim.
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if (NumSubOps == 1 || (InstOpRec->getValue("ParserMatchClass") &&
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InstOpRec->getValueAsDef("ParserMatchClass")
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->getValueAsString("Name") != "Imm")) {
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ResultOperands.push_back(ResOp);
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ResultInstOperandIndex.push_back(std::pair(i, -1));
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++AliasOpNo;
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// Otherwise, we need to match each of the suboperands individually.
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} else {
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DagInit *MIOI = ResultInst->Operands[i].MIOperandInfo;
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for (unsigned SubOp = 0; SubOp != NumSubOps; ++SubOp) {
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Record *SubRec = cast<DefInit>(MIOI->getArg(SubOp))->getDef();
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// Take care to instantiate each of the suboperands with the correct
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// nomenclature: $foo.bar
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ResultOperands.emplace_back(
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Result->getArgName(AliasOpNo)->getAsUnquotedString() + "." +
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MIOI->getArgName(SubOp)->getAsUnquotedString(),
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SubRec);
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ResultInstOperandIndex.push_back(std::pair(i, SubOp));
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}
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++AliasOpNo;
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}
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continue;
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}
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// If the argument did not match the instruction operand, and the operand
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// is composed of multiple suboperands, try matching the suboperands.
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if (NumSubOps > 1) {
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DagInit *MIOI = ResultInst->Operands[i].MIOperandInfo;
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for (unsigned SubOp = 0; SubOp != NumSubOps; ++SubOp) {
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if (AliasOpNo >= Result->getNumArgs())
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PrintFatalError(R->getLoc(), "not enough arguments for instruction!");
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Record *SubRec = cast<DefInit>(MIOI->getArg(SubOp))->getDef();
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if (tryAliasOpMatch(Result, AliasOpNo, SubRec, false, R->getLoc(), T,
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ResOp)) {
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ResultOperands.push_back(ResOp);
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ResultInstOperandIndex.push_back(std::pair(i, SubOp));
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++AliasOpNo;
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} else {
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PrintFatalError(
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R->getLoc(),
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"result argument #" + Twine(AliasOpNo) +
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" does not match instruction operand class " +
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(SubOp == 0 ? InstOpRec->getName() : SubRec->getName()));
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}
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}
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continue;
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}
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PrintFatalError(R->getLoc(),
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"result argument #" + Twine(AliasOpNo) +
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" does not match instruction operand class " +
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InstOpRec->getName());
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}
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if (AliasOpNo != Result->getNumArgs())
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PrintFatalError(R->getLoc(), "too many operands for instruction!");
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}
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