f6076bd81f
1. When converting from the GPU dialect to the ROCDL dialect, if the
function that contains a gpu.thread_id or gpu.block_id op is annotated
with gpu.known_{block,grid}_size, use that size to set a "range"
attribute on the corresponding rocdl intrinsic so that the LLVM
frontend can optimize based on that range information.
1b. When translating from the rocdl dialect to LLVM IR, use the
"range" attribute, if present, to set !range metadata on the relevant
function call.
2. Deprecate the old rocdl.max_flat_work_group_size attribute, which
was used in a tensorflow backend. Instead, use
rocdl.flat_work_group_size going forward to allow kernel generators to
specify the minimum and maximum work group sizes a kernel may be
launched with in one attribute, thus more closely matching the backend.
3. When translating from gpu.func to llvm.func within gpu-to-rocdl,
copy the known_block_size attribute as rocdl.reqd_work_group_size to
enable further translations to set the corresponding metadata on the
LLVM IR function. Also, set the rocdl.flat_work_group_size attribute
to ensure that the reqd_work_group_size metadata and the
amdgpu-flat-work-group-size metadata are consistent.
3b. Extend the ROCDL to LLVM IR translation to set the
!reqd_work_group_size metadata on LLVM functions
Also update tests and add functions to the ROCDL dialect to ensure
attribute names are used consistently.
Depends on D139865
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D139866
89 lines
3.4 KiB
C++
89 lines
3.4 KiB
C++
//===- IndexIntrinsicsOpLowering.h - GPU IndexOps Lowering class *- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef MLIR_CONVERSION_GPUCOMMON_INDEXINTRINSICSOPLOWERING_H_
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#define MLIR_CONVERSION_GPUCOMMON_INDEXINTRINSICSOPLOWERING_H_
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#include "mlir/Conversion/LLVMCommon/Pattern.h"
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#include "mlir/Dialect/GPU/IR/GPUDialect.h"
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#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
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#include "mlir/IR/BuiltinAttributes.h"
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namespace mlir {
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// Rewriting that replaces Op with XOp, YOp, or ZOp depending on the dimension
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// that Op operates on. Op is assumed to return an `index` value and
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// XOp, YOp and ZOp are assumed to return an `llvm.i32` value. Depending on
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// `indexBitwidth`, sign-extend or truncate the resulting value to match the
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// bitwidth expected by the consumers of the value.
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template <typename Op, typename XOp, typename YOp, typename ZOp>
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struct GPUIndexIntrinsicOpLowering : public ConvertOpToLLVMPattern<Op> {
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private:
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unsigned indexBitwidth;
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StringRef boundsAttrName;
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public:
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explicit GPUIndexIntrinsicOpLowering(LLVMTypeConverter &typeConverter)
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: ConvertOpToLLVMPattern<Op>(typeConverter),
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indexBitwidth(typeConverter.getIndexTypeBitwidth()),
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boundsAttrName("") {}
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explicit GPUIndexIntrinsicOpLowering(LLVMTypeConverter &typeConverter,
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StringRef boundsAttrName)
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: ConvertOpToLLVMPattern<Op>(typeConverter),
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indexBitwidth(typeConverter.getIndexTypeBitwidth()),
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boundsAttrName(boundsAttrName) {}
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// Convert the kernel arguments to an LLVM type, preserve the rest.
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LogicalResult
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matchAndRewrite(Op op, typename Op::Adaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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auto loc = op->getLoc();
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MLIRContext *context = rewriter.getContext();
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Operation *newOp;
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switch (op.getDimension()) {
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case gpu::Dimension::x:
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newOp = rewriter.create<XOp>(loc, IntegerType::get(context, 32));
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break;
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case gpu::Dimension::y:
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newOp = rewriter.create<YOp>(loc, IntegerType::get(context, 32));
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break;
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case gpu::Dimension::z:
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newOp = rewriter.create<ZOp>(loc, IntegerType::get(context, 32));
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break;
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}
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Operation *function;
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if (auto gpuFunc = op->template getParentOfType<gpu::GPUFuncOp>())
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function = gpuFunc;
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if (auto llvmFunc = op->template getParentOfType<LLVM::LLVMFuncOp>())
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function = llvmFunc;
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if (!boundsAttrName.empty() && function) {
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if (auto attr = function->template getAttrOfType<DenseI32ArrayAttr>(
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boundsAttrName)) {
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int32_t maximum = attr[static_cast<uint32_t>(op.getDimension())];
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newOp->setAttr("range", rewriter.getDenseI32ArrayAttr({0, maximum}));
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}
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}
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if (indexBitwidth > 32) {
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newOp = rewriter.create<LLVM::SExtOp>(
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loc, IntegerType::get(context, indexBitwidth), newOp->getResult(0));
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} else if (indexBitwidth < 32) {
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newOp = rewriter.create<LLVM::TruncOp>(
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loc, IntegerType::get(context, indexBitwidth), newOp->getResult(0));
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}
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rewriter.replaceOp(op, newOp->getResults());
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return success();
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}
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};
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} // namespace mlir
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#endif // MLIR_CONVERSION_GPUCOMMON_INDEXINTRINSICSOPLOWERING_H_
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