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dda73336ad22bd0b5ecda17040c50fb10fcbe5fb
clang-p2996/mlir/test/Dialect/ArmSVE
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Benjamin Maxwell 7dcca62132 [mlir][ArmSVE] Add arm_sve.zip.x2 and arm_sve.zip.x4 ops (#81278)
This adds ops for the two and four-way SME 2 multi-vector zips.

See:

-
https://developer.arm.com/documentation/ddi0602/2023-12/SME-Instructions/ZIP--two-registers---Interleave-elements-from-two-vectors-?lang=en
-
https://developer.arm.com/documentation/ddi0602/2023-12/SME-Instructions/ZIP--four-registers---Interleave-elements-from-four-vectors-?lang=en
2024-02-16 11:34:34 +00:00
..
invalid.mlir
[mlir][ArmSVE] Add arm_sve.zip.x2 and arm_sve.zip.x4 ops (#81278)
2024-02-16 11:34:34 +00:00
legalize-for-llvm.mlir
[mlir][ArmSVE] Add arm_sve.zip.x2 and arm_sve.zip.x4 ops (#81278)
2024-02-16 11:34:34 +00:00
legalize-vector-storage.mlir
…
roundtrip.mlir
[mlir][ArmSVE] Add arm_sve.zip.x2 and arm_sve.zip.x4 ops (#81278)
2024-02-16 11:34:34 +00:00
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