ace69e6b94
This PR improves the documentation for the `gpu-lower-to-nvvm-pipeline` (as it was remaning item for #75775) - Changes pipeline `gpu-lower-to-nvvm` -> `gpu-lower-to-nvvm-pipeline` - Adds a section in GPU Dialect in website. It clarifies the pipeline's functionality in lowering primary dialects to NVVM targets.
38 lines
1.4 KiB
MLIR
38 lines
1.4 KiB
MLIR
// RUN: mlir-opt %s \
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// RUN: | mlir-opt -gpu-lower-to-nvvm-pipeline="cubin-format=%gpu_compilation_format" \
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// RUN: | mlir-cpu-runner \
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// RUN: --shared-libs=%mlir_cuda_runtime \
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// RUN: --shared-libs=%mlir_runner_utils \
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// RUN: --entry-point-result=void \
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// RUN: | FileCheck %s
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// CHECK: [4, 5, 6, 7, 0, 1, 2, 3, 12, -1, -1, -1, 8]
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func.func @main() {
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%arg = memref.alloc() : memref<13xf32>
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%dst = memref.cast %arg : memref<13xf32> to memref<?xf32>
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%one = arith.constant 1 : index
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%c0 = arith.constant 0 : index
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%sx = memref.dim %dst, %c0 : memref<?xf32>
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%cast_dst = memref.cast %dst : memref<?xf32> to memref<*xf32>
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gpu.host_register %cast_dst : memref<*xf32>
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gpu.launch blocks(%bx, %by, %bz) in (%grid_x = %one, %grid_y = %one, %grid_z = %one)
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threads(%tx, %ty, %tz) in (%block_x = %sx, %block_y = %one, %block_z = %one) {
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%t0 = arith.index_cast %tx : index to i32
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%val = arith.sitofp %t0 : i32 to f32
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%width = arith.index_cast %block_x : index to i32
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%offset = arith.constant 4 : i32
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%shfl, %valid = gpu.shuffle xor %val, %offset, %width : f32
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cf.cond_br %valid, ^bb1(%shfl : f32), ^bb0
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^bb0:
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%m1 = arith.constant -1.0 : f32
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cf.br ^bb1(%m1 : f32)
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^bb1(%value : f32):
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memref.store %value, %dst[%tx] : memref<?xf32>
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gpu.terminator
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}
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call @printMemrefF32(%cast_dst) : (memref<*xf32>) -> ()
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return
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}
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func.func private @printMemrefF32(%ptr : memref<*xf32>)
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