7a2fdc685f
This patch creates the ArmSME dialect, and provides the intrinsic op definition necessary for lowering to LLVM IR. This will cover most instructions interacting with the ZA tile register, not covering SME2 instructions. Source: https://developer.arm.com/documentation/ddi0616/latest Reviewed By: awarzynski, c-rhodes Differential Revision: https://reviews.llvm.org/D152878
48 lines
1.1 KiB
MLIR
48 lines
1.1 KiB
MLIR
// RUN: echo "" | mlir-opt --show-dialects | FileCheck %s
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// CHECK: Available Dialects:
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// CHECK-SAME: acc
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// CHECK-SAME: affine
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// CHECK-SAME: amdgpu
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// CHECK-SAME: amx
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// CHECK-SAME: arith
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// CHECK-SAME: arm_neon
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// CHECK-SAME: arm_sme
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// CHECK-SAME: arm_sve
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// CHECK-SAME: async
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// CHECK-SAME: bufferization
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// CHECK-SAME: builtin
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// CHECK-SAME: cf
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// CHECK-SAME: complex
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// CHECK-SAME: dlti
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// CHECK-SAME: emitc
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// CHECK-SAME: func
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// CHECK-SAME: gpu
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// CHECK-SAME: index
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// CHECK-SAME: irdl
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// CHECK-SAME: linalg
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// CHECK-SAME: llvm
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// CHECK-SAME: math
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// CHECK-SAME: memref
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// CHECK-SAME: ml_program
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// CHECK-SAME: nvgpu
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// CHECK-SAME: nvvm
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// CHECK-SAME: omp
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// CHECK-SAME: pdl
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// CHECK-SAME: pdl_interp
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// CHECK-SAME: quant
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// CHECK-SAME: rocdl
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// CHECK-SAME: scf
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// CHECK-SAME: shape
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// CHECK-SAME: sparse_tensor
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// CHECK-SAME: spirv
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// CHECK-SAME: tensor
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// CHECK-SAME: test
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// CHECK-SAME: test_dyn
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// CHECK-SAME: tosa
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// CHECK-SAME: transform
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// CHECK-SAME: vector
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// CHECK-SAME: x86vector
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// RUN: mlir-opt --help-hidden | FileCheck %s -check-prefix=CHECK-HELP
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// CHECK-HELP: -p - Alias for --pass-pipeline
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