33c0f93f6c
This infrastructure has proven proven its worth, so give it a more prominent place. My immediate motivation for this is the desire to reuse this infrastructure for qemu platform testing, but I believe this move makes sense independently of that. Moving this code to the packages tree will allow as to add more structure to the gdb client tests -- currently they are all crammed into the same test folder as that was the only way they could access this code. I'm splitting the code into two parts while moving it. The first once contains just the generic gdb protocol wrappers, while the other one contains the unit test glue. The reason for that is that for qemu testing, I need to run the gdb code in a separate process, so I will only be using the first part there. Differential Revision: https://reviews.llvm.org/D113893
242 lines
10 KiB
Python
242 lines
10 KiB
Python
from __future__ import print_function
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import lldb
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from lldbsuite.test.lldbtest import *
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from lldbsuite.test.decorators import *
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from lldbsuite.test.gdbclientutils import *
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from lldbsuite.test.lldbgdbclient import GDBRemoteTestBase
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class TestNestedRegDefinitions(GDBRemoteTestBase):
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mydir = TestBase.compute_mydir(__file__)
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@skipIfXmlSupportMissing
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@skipIfRemote
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def test(self):
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"""
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Test lldb's parsing of the <architecture> tag in the target.xml register
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description packet.
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"""
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class MyResponder(MockGDBServerResponder):
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def qXferRead(self, obj, annex, offset, length):
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if annex == "target.xml":
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return """<?xml version="1.0"?><!DOCTYPE target SYSTEM "gdb-target.dtd"><target><architecture>i386:x86-64</architecture><xi:include href="i386-64bit.xml"/></target>""", False
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if annex == "i386-64bit.xml":
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return """<?xml version="1.0"?>
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<!-- Copyright (C) 2010-2017 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved. -->
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<!-- I386 64bit -->
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<!DOCTYPE target SYSTEM "gdb-target.dtd">
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<feature name="org.gnu.gdb.i386.64bit">
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<xi:include href="i386-64bit-core.xml"/>
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<xi:include href="i386-64bit-sse.xml"/>
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</feature>""", False
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if annex == "i386-64bit-core.xml":
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return """<?xml version="1.0"?>
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<!-- Copyright (C) 2010-2015 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved. -->
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<!DOCTYPE feature SYSTEM "gdb-target.dtd">
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<feature name="org.gnu.gdb.i386.core">
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<flags id="i386_eflags" size="4">
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<field name="CF" start="0" end="0"/>
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<field name="" start="1" end="1"/>
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<field name="PF" start="2" end="2"/>
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<field name="AF" start="4" end="4"/>
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<field name="ZF" start="6" end="6"/>
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<field name="SF" start="7" end="7"/>
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<field name="TF" start="8" end="8"/>
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<field name="IF" start="9" end="9"/>
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<field name="DF" start="10" end="10"/>
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<field name="OF" start="11" end="11"/>
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<field name="NT" start="14" end="14"/>
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<field name="RF" start="16" end="16"/>
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<field name="VM" start="17" end="17"/>
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<field name="AC" start="18" end="18"/>
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<field name="VIF" start="19" end="19"/>
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<field name="VIP" start="20" end="20"/>
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<field name="ID" start="21" end="21"/>
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</flags>
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<reg name="rax" bitsize="64" type="int64"/>
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<reg name="rbx" bitsize="64" type="int64"/>
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<reg name="rcx" bitsize="64" type="int64"/>
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<reg name="rdx" bitsize="64" type="int64"/>
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<reg name="rsi" bitsize="64" type="int64"/>
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<reg name="rdi" bitsize="64" type="int64"/>
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<reg name="rbp" bitsize="64" type="data_ptr"/>
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<reg name="rsp" bitsize="64" type="data_ptr"/>
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<reg name="r8" bitsize="64" type="int64"/>
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<reg name="r9" bitsize="64" type="int64"/>
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<reg name="r10" bitsize="64" type="int64"/>
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<reg name="r11" bitsize="64" type="int64"/>
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<reg name="r12" bitsize="64" type="int64"/>
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<reg name="r13" bitsize="64" type="int64"/>
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<reg name="r14" bitsize="64" type="int64"/>
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<reg name="r15" bitsize="64" type="int64"/>
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<reg name="rip" bitsize="64" type="code_ptr"/>
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<reg name="eflags" bitsize="32" type="i386_eflags"/>
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<reg name="cs" bitsize="32" type="int32"/>
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<reg name="ss" bitsize="32" type="int32"/>
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<reg name="ds" bitsize="32" type="int32"/>
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<reg name="es" bitsize="32" type="int32"/>
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<reg name="fs" bitsize="32" type="int32"/>
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<reg name="gs" bitsize="32" type="int32"/>
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<reg name="st0" bitsize="80" type="i387_ext"/>
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<reg name="st1" bitsize="80" type="i387_ext"/>
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<reg name="st2" bitsize="80" type="i387_ext"/>
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<reg name="st3" bitsize="80" type="i387_ext"/>
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<reg name="st4" bitsize="80" type="i387_ext"/>
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<reg name="st5" bitsize="80" type="i387_ext"/>
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<reg name="st6" bitsize="80" type="i387_ext"/>
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<reg name="st7" bitsize="80" type="i387_ext"/>
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<reg name="fctrl" bitsize="32" type="int" group="float"/>
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<reg name="fstat" bitsize="32" type="int" group="float"/>
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<reg name="ftag" bitsize="32" type="int" group="float"/>
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<reg name="fiseg" bitsize="32" type="int" group="float"/>
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<reg name="fioff" bitsize="32" type="int" group="float"/>
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<reg name="foseg" bitsize="32" type="int" group="float"/>
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<reg name="fooff" bitsize="32" type="int" group="float"/>
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<reg name="fop" bitsize="32" type="int" group="float"/>
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</feature>""", False
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if annex == "i386-64bit-sse.xml":
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return """<?xml version="1.0"?>
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<!-- Copyright (C) 2010-2017 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved. -->
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<!DOCTYPE feature SYSTEM "gdb-target.dtd">
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<feature name="org.gnu.gdb.i386.64bit.sse">
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<vector id="v4f" type="ieee_single" count="4"/>
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<vector id="v2d" type="ieee_double" count="2"/>
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<vector id="v16i8" type="int8" count="16"/>
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<vector id="v8i16" type="int16" count="8"/>
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<vector id="v4i32" type="int32" count="4"/>
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<vector id="v2i64" type="int64" count="2"/>
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<union id="vec128">
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<field name="v4_float" type="v4f"/>
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<field name="v2_double" type="v2d"/>
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<field name="v16_int8" type="v16i8"/>
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<field name="v8_int16" type="v8i16"/>
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<field name="v4_int32" type="v4i32"/>
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<field name="v2_int64" type="v2i64"/>
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<field name="uint128" type="uint128"/>
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</union>
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<flags id="i386_mxcsr" size="4">
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<field name="IE" start="0" end="0"/>
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<field name="DE" start="1" end="1"/>
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<field name="ZE" start="2" end="2"/>
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<field name="OE" start="3" end="3"/>
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<field name="UE" start="4" end="4"/>
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<field name="PE" start="5" end="5"/>
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<field name="DAZ" start="6" end="6"/>
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<field name="IM" start="7" end="7"/>
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<field name="DM" start="8" end="8"/>
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<field name="ZM" start="9" end="9"/>
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<field name="OM" start="10" end="10"/>
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<field name="UM" start="11" end="11"/>
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<field name="PM" start="12" end="12"/>
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<field name="FZ" start="15" end="15"/>
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</flags>
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<reg name="xmm0" bitsize="128" type="vec128" regnum="40"/>
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<reg name="xmm1" bitsize="128" type="vec128"/>
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<reg name="xmm2" bitsize="128" type="vec128"/>
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<reg name="xmm3" bitsize="128" type="vec128"/>
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<reg name="xmm4" bitsize="128" type="vec128"/>
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<reg name="xmm5" bitsize="128" type="vec128"/>
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<reg name="xmm6" bitsize="128" type="vec128"/>
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<reg name="xmm7" bitsize="128" type="vec128"/>
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<reg name="xmm8" bitsize="128" type="vec128"/>
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<reg name="xmm9" bitsize="128" type="vec128"/>
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<reg name="xmm10" bitsize="128" type="vec128"/>
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<reg name="xmm11" bitsize="128" type="vec128"/>
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<reg name="xmm12" bitsize="128" type="vec128"/>
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<reg name="xmm13" bitsize="128" type="vec128"/>
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<reg name="xmm14" bitsize="128" type="vec128"/>
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<reg name="xmm15" bitsize="128" type="vec128"/>
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<reg name="mxcsr" bitsize="32" type="i386_mxcsr" group="vector"/>
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</feature>""", False
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return None, False
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def readRegister(self, regnum):
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return ""
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def readRegisters(self):
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return "0600000000000000c0b7c00080fffffff021c60080ffffff1a00000000000000020000000000000078b7c00080ffffff203f8ca090ffffff103f8ca090ffffff3025990a80ffffff809698000000000070009f0a80ffffff020000000000000000eae10080ffffff00000000000000001822d74f1a00000078b7c00080ffffff0e12410080ffff004602000008000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007f0300000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000801f0000"
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def haltReason(self):
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return "T02thread:dead;threads:dead;"
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def qfThreadInfo(self):
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return "mdead"
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def qC(self):
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return ""
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def qSupported(self, client_supported):
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return "PacketSize=4000;qXfer:features:read+"
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def QThreadSuffixSupported(self):
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return "OK"
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def QListThreadsInStopReply(self):
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return "OK"
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self.server.responder = MyResponder()
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if self.TraceOn():
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self.runCmd("log enable gdb-remote packets")
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self.addTearDownHook(
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lambda: self.runCmd("log disable gdb-remote packets"))
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target = self.dbg.CreateTargetWithFileAndArch(None, None)
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process = self.connect(target)
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if self.TraceOn():
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interp = self.dbg.GetCommandInterpreter()
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result = lldb.SBCommandReturnObject()
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interp.HandleCommand("target list", result)
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print(result.GetOutput())
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rip_valobj = process.GetThreadAtIndex(0).GetFrameAtIndex(0).FindRegister("rip")
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self.assertEqual(rip_valobj.GetValueAsUnsigned(), 0x00ffff800041120e)
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r15_valobj = process.GetThreadAtIndex(0).GetFrameAtIndex(0).FindRegister("r15")
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self.assertEqual(r15_valobj.GetValueAsUnsigned(), 0xffffff8000c0b778)
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mxcsr_valobj = process.GetThreadAtIndex(0).GetFrameAtIndex(0).FindRegister("mxcsr")
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self.assertEqual(mxcsr_valobj.GetValueAsUnsigned(), 0x00001f80)
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gpr_reg_set_name = process.GetThreadAtIndex(0).GetFrameAtIndex(0).GetRegisters().GetValueAtIndex(0).GetName()
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self.assertEqual(gpr_reg_set_name, "general")
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float_reg_set_name = process.GetThreadAtIndex(0).GetFrameAtIndex(0).GetRegisters().GetValueAtIndex(1).GetName()
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self.assertEqual(float_reg_set_name, "float")
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vector_reg_set_name = process.GetThreadAtIndex(0).GetFrameAtIndex(0).GetRegisters().GetValueAtIndex(2).GetName()
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self.assertEqual(vector_reg_set_name, "vector")
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if self.TraceOn():
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print("rip is 0x%x" % rip_valobj.GetValueAsUnsigned())
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print("r15 is 0x%x" % r15_valobj.GetValueAsUnsigned())
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print("mxcsr is 0x%x" % mxcsr_valobj.GetValueAsUnsigned())
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