0bf5846553
The main difference is that it's possible for multiple change observers to be installed at the same time whereas there can only be one MachineFunction delegate installed. This allows downstream targets to continue to use observers to recursively select. The target in question was selecting a gMIR instruction to a machine instruction plus some gMIR around it and relying on observers to ensure it correctly selected any gMIR it created before returning to the main loop.
390 lines
14 KiB
C++
390 lines
14 KiB
C++
//===- llvm/CodeGen/GlobalISel/InstructionSelect.cpp - InstructionSelect ---==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the InstructionSelect class.
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
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#include "llvm/ADT/PostOrderIterator.h"
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#include "llvm/ADT/ScopeExit.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/Analysis/LazyBlockFrequencyInfo.h"
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#include "llvm/Analysis/ProfileSummaryInfo.h"
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#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
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#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/Config/config.h"
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#include "llvm/IR/Function.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/CodeGenCoverage.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/DebugCounter.h"
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#include "llvm/Target/TargetMachine.h"
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#define DEBUG_TYPE "instruction-select"
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using namespace llvm;
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DEBUG_COUNTER(GlobalISelCounter, "globalisel",
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"Controls whether to select function with GlobalISel");
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#ifdef LLVM_GISEL_COV_PREFIX
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static cl::opt<std::string>
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CoveragePrefix("gisel-coverage-prefix", cl::init(LLVM_GISEL_COV_PREFIX),
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cl::desc("Record GlobalISel rule coverage files of this "
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"prefix if instrumentation was generated"));
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#else
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static const std::string CoveragePrefix;
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#endif
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char InstructionSelect::ID = 0;
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INITIALIZE_PASS_BEGIN(InstructionSelect, DEBUG_TYPE,
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"Select target instructions out of generic instructions",
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false, false)
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INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
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INITIALIZE_PASS_DEPENDENCY(GISelKnownBitsAnalysis)
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INITIALIZE_PASS_DEPENDENCY(ProfileSummaryInfoWrapperPass)
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INITIALIZE_PASS_DEPENDENCY(LazyBlockFrequencyInfoPass)
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INITIALIZE_PASS_END(InstructionSelect, DEBUG_TYPE,
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"Select target instructions out of generic instructions",
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false, false)
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InstructionSelect::InstructionSelect(CodeGenOptLevel OL, char &PassID)
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: MachineFunctionPass(PassID), OptLevel(OL) {}
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/// This class observes instruction insertions/removals.
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/// InstructionSelect stores an iterator of the instruction prior to the one
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/// that is currently being selected to determine which instruction to select
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/// next. Previously this meant that selecting multiple instructions at once was
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/// illegal behavior due to potential invalidation of this iterator. This is
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/// a non-obvious limitation for selector implementers. Therefore, to allow
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/// deletion of arbitrary instructions, we detect this case and continue
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/// selection with the predecessor of the deleted instruction.
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class InstructionSelect::MIIteratorMaintainer : public GISelChangeObserver {
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#ifndef NDEBUG
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SmallSetVector<const MachineInstr *, 32> CreatedInstrs;
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#endif
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public:
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MachineBasicBlock::reverse_iterator MII;
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void changingInstr(MachineInstr &MI) override {
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llvm_unreachable("InstructionSelect does not track changed instructions!");
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}
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void changedInstr(MachineInstr &MI) override {
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llvm_unreachable("InstructionSelect does not track changed instructions!");
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}
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void createdInstr(MachineInstr &MI) override {
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LLVM_DEBUG(dbgs() << "Creating: " << MI; CreatedInstrs.insert(&MI));
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}
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void erasingInstr(MachineInstr &MI) override {
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LLVM_DEBUG(dbgs() << "Erasing: " << MI; CreatedInstrs.remove(&MI));
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if (MII.getInstrIterator().getNodePtr() == &MI) {
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// If the iterator points to the MI that will be erased (i.e. the MI prior
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// to the MI that is currently being selected), the iterator would be
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// invalidated. Continue selection with its predecessor.
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++MII;
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LLVM_DEBUG(dbgs() << "Instruction removal updated iterator.\n");
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}
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}
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void reportFullyCreatedInstrs() {
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LLVM_DEBUG({
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if (CreatedInstrs.empty()) {
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dbgs() << "Created no instructions.\n";
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} else {
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dbgs() << "Created:\n";
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for (const auto *MI : CreatedInstrs) {
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dbgs() << " " << *MI;
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}
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CreatedInstrs.clear();
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}
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});
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}
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};
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void InstructionSelect::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<TargetPassConfig>();
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AU.addRequired<GISelKnownBitsAnalysis>();
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AU.addPreserved<GISelKnownBitsAnalysis>();
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if (OptLevel != CodeGenOptLevel::None) {
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AU.addRequired<ProfileSummaryInfoWrapperPass>();
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LazyBlockFrequencyInfoPass::getLazyBFIAnalysisUsage(AU);
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}
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getSelectionDAGFallbackAnalysisUsage(AU);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
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// If the ISel pipeline failed, do not bother running that pass.
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if (MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::FailedISel))
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return false;
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ISel = MF.getSubtarget().getInstructionSelector();
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ISel->TPC = &getAnalysis<TargetPassConfig>();
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// FIXME: Properly override OptLevel in TargetMachine. See OptLevelChanger
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CodeGenOptLevel OldOptLevel = OptLevel;
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auto RestoreOptLevel = make_scope_exit([=]() { OptLevel = OldOptLevel; });
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OptLevel = MF.getFunction().hasOptNone() ? CodeGenOptLevel::None
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: MF.getTarget().getOptLevel();
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KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
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if (OptLevel != CodeGenOptLevel::None) {
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PSI = &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
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if (PSI && PSI->hasProfileSummary())
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BFI = &getAnalysis<LazyBlockFrequencyInfoPass>().getBFI();
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}
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return selectMachineFunction(MF);
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}
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bool InstructionSelect::selectMachineFunction(MachineFunction &MF) {
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LLVM_DEBUG(dbgs() << "Selecting function: " << MF.getName() << '\n');
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assert(ISel && "Cannot work without InstructionSelector");
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const TargetPassConfig &TPC = *ISel->TPC;
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CodeGenCoverage CoverageInfo;
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ISel->setupMF(MF, KB, &CoverageInfo, PSI, BFI);
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// An optimization remark emitter. Used to report failures.
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MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);
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ISel->MORE = &MORE;
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// FIXME: There are many other MF/MFI fields we need to initialize.
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MachineRegisterInfo &MRI = MF.getRegInfo();
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#ifndef NDEBUG
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// Check that our input is fully legal: we require the function to have the
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// Legalized property, so it should be.
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// FIXME: This should be in the MachineVerifier, as the RegBankSelected
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// property check already is.
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if (!DisableGISelLegalityCheck)
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if (const MachineInstr *MI = machineFunctionIsIllegal(MF)) {
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reportGISelFailure(MF, TPC, MORE, "gisel-select",
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"instruction is not legal", *MI);
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return false;
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}
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// FIXME: We could introduce new blocks and will need to fix the outer loop.
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// Until then, keep track of the number of blocks to assert that we don't.
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const size_t NumBlocks = MF.size();
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#endif
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// Keep track of selected blocks, so we can delete unreachable ones later.
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DenseSet<MachineBasicBlock *> SelectedBlocks;
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{
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// Observe IR insertions and removals during selection.
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// We only install a MachineFunction::Delegate instead of a
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// GISelChangeObserver, because we do not want notifications about changed
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// instructions. This prevents significant compile-time regressions from
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// e.g. constrainOperandRegClass().
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GISelObserverWrapper AllObservers;
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MIIteratorMaintainer MIIMaintainer;
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AllObservers.addObserver(&MIIMaintainer);
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RAIIDelegateInstaller DelInstaller(MF, &AllObservers);
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ISel->AllObservers = &AllObservers;
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for (MachineBasicBlock *MBB : post_order(&MF)) {
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ISel->CurMBB = MBB;
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SelectedBlocks.insert(MBB);
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// Select instructions in reverse block order.
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MIIMaintainer.MII = MBB->rbegin();
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for (auto End = MBB->rend(); MIIMaintainer.MII != End;) {
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MachineInstr &MI = *MIIMaintainer.MII;
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// Increment early to skip instructions inserted by select().
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++MIIMaintainer.MII;
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LLVM_DEBUG(dbgs() << "\nSelect: " << MI);
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if (!selectInstr(MI)) {
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LLVM_DEBUG(dbgs() << "Selection failed!\n";
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MIIMaintainer.reportFullyCreatedInstrs());
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reportGISelFailure(MF, TPC, MORE, "gisel-select", "cannot select",
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MI);
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return false;
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}
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LLVM_DEBUG(MIIMaintainer.reportFullyCreatedInstrs());
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}
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}
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}
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for (MachineBasicBlock &MBB : MF) {
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if (MBB.empty())
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continue;
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if (!SelectedBlocks.contains(&MBB)) {
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// This is an unreachable block and therefore hasn't been selected, since
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// the main selection loop above uses a postorder block traversal.
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// We delete all the instructions in this block since it's unreachable.
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MBB.clear();
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// Don't delete the block in case the block has it's address taken or is
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// still being referenced by a phi somewhere.
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continue;
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}
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// Try to find redundant copies b/w vregs of the same register class.
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for (auto MII = MBB.rbegin(), End = MBB.rend(); MII != End;) {
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MachineInstr &MI = *MII;
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++MII;
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if (MI.getOpcode() != TargetOpcode::COPY)
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continue;
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Register SrcReg = MI.getOperand(1).getReg();
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Register DstReg = MI.getOperand(0).getReg();
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if (SrcReg.isVirtual() && DstReg.isVirtual()) {
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auto SrcRC = MRI.getRegClass(SrcReg);
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auto DstRC = MRI.getRegClass(DstReg);
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if (SrcRC == DstRC) {
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MRI.replaceRegWith(DstReg, SrcReg);
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MI.eraseFromParent();
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}
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}
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}
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}
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#ifndef NDEBUG
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const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
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// Now that selection is complete, there are no more generic vregs. Verify
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// that the size of the now-constrained vreg is unchanged and that it has a
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// register class.
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for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
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Register VReg = Register::index2VirtReg(I);
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MachineInstr *MI = nullptr;
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if (!MRI.def_empty(VReg))
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MI = &*MRI.def_instr_begin(VReg);
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else if (!MRI.use_empty(VReg)) {
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MI = &*MRI.use_instr_begin(VReg);
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// Debug value instruction is permitted to use undefined vregs.
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if (MI->isDebugValue())
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continue;
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}
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if (!MI)
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continue;
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const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg);
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if (!RC) {
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reportGISelFailure(MF, TPC, MORE, "gisel-select",
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"VReg has no regclass after selection", *MI);
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return false;
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}
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const LLT Ty = MRI.getType(VReg);
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if (Ty.isValid() &&
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TypeSize::isKnownGT(Ty.getSizeInBits(), TRI.getRegSizeInBits(*RC))) {
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reportGISelFailure(
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MF, TPC, MORE, "gisel-select",
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"VReg's low-level type and register class have different sizes", *MI);
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return false;
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}
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}
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if (MF.size() != NumBlocks) {
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MachineOptimizationRemarkMissed R("gisel-select", "GISelFailure",
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MF.getFunction().getSubprogram(),
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/*MBB=*/nullptr);
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R << "inserting blocks is not supported yet";
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reportGISelFailure(MF, TPC, MORE, R);
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return false;
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}
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#endif
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if (!DebugCounter::shouldExecute(GlobalISelCounter)) {
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dbgs() << "Falling back for function " << MF.getName() << "\n";
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MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
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return false;
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}
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// Determine if there are any calls in this machine function. Ported from
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// SelectionDAG.
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MachineFrameInfo &MFI = MF.getFrameInfo();
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for (const auto &MBB : MF) {
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if (MFI.hasCalls() && MF.hasInlineAsm())
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break;
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for (const auto &MI : MBB) {
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if ((MI.isCall() && !MI.isReturn()) || MI.isStackAligningInlineAsm())
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MFI.setHasCalls(true);
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if (MI.isInlineAsm())
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MF.setHasInlineAsm(true);
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}
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}
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// FIXME: FinalizeISel pass calls finalizeLowering, so it's called twice.
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auto &TLI = *MF.getSubtarget().getTargetLowering();
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TLI.finalizeLowering(MF);
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LLVM_DEBUG({
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dbgs() << "Rules covered by selecting function: " << MF.getName() << ":";
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for (auto RuleID : CoverageInfo.covered())
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dbgs() << " id" << RuleID;
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dbgs() << "\n\n";
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});
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CoverageInfo.emit(CoveragePrefix,
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TLI.getTargetMachine().getTarget().getBackendName());
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// If we successfully selected the function nothing is going to use the vreg
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// types after us (otherwise MIRPrinter would need them). Make sure the types
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// disappear.
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MRI.clearVirtRegTypes();
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// FIXME: Should we accurately track changes?
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return true;
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}
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bool InstructionSelect::selectInstr(MachineInstr &MI) {
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MachineRegisterInfo &MRI = ISel->MF->getRegInfo();
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// We could have folded this instruction away already, making it dead.
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// If so, erase it.
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if (isTriviallyDead(MI, MRI)) {
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LLVM_DEBUG(dbgs() << "Is dead.\n");
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salvageDebugInfo(MRI, MI);
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MI.eraseFromParent();
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return true;
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}
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// Eliminate hints or G_CONSTANT_FOLD_BARRIER.
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if (isPreISelGenericOptimizationHint(MI.getOpcode()) ||
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MI.getOpcode() == TargetOpcode::G_CONSTANT_FOLD_BARRIER) {
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auto [DstReg, SrcReg] = MI.getFirst2Regs();
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// At this point, the destination register class of the op may have
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// been decided.
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//
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// Propagate that through to the source register.
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const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg);
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if (DstRC)
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MRI.setRegClass(SrcReg, DstRC);
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assert(canReplaceReg(DstReg, SrcReg, MRI) &&
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"Must be able to replace dst with src!");
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MI.eraseFromParent();
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MRI.replaceRegWith(DstReg, SrcReg);
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return true;
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}
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if (MI.getOpcode() == TargetOpcode::G_INVOKE_REGION_START) {
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MI.eraseFromParent();
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return true;
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}
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return ISel->select(MI);
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}
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