clang-p2996

AsmParser

[NFC] Update function names in MCTargetAsmParser.h (#108643 )

2024-09-18 11:43:49 -04:00

Disassembler

[RISCV] Fix fneg.d/fabs.d aliasing handling for Zdinx. Add missing fmv.s/d aliases.

2024-09-10 11:44:04 -07:00

GISel

[RISCV][GISel] Use libcalls for rint, nearbyint, trunc, round, and roundeven intrinsics. (#108779 )

2024-09-18 12:07:44 -07:00

MCA

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MCTargetDesc

[RISCV] Remove unneeded check for NoRegister from RISCVInstPrinter::printRegReg. NFC

2024-09-14 20:10:57 -07:00

TargetInfo

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CMakeLists.txt

[RISCV][GISEL] Introduce the RISCVPostLegalizerLowering pass (#108991 )

2024-09-17 13:18:35 -04:00

RISCV.h

[RISCV][GISEL] Introduce the RISCVPostLegalizerLowering pass (#108991 )

2024-09-17 13:18:35 -04:00

RISCV.td

[RISCV] Add scheduling model for Syntacore SCR7 (#108814 )

2024-09-17 18:52:55 +03:00

RISCVAsmPrinter.cpp

[RISCV] Support the large code model. (#70308 )

2024-09-09 09:15:07 +08:00

RISCVCallingConv.cpp

[RISCV] Use CCValAssign::getCustomReg for fixed vector arguments/returns with RVV. (#108470 )

2024-09-13 07:23:44 -07:00

RISCVCallingConv.h

[RISCV] Reduce the interface to RISCVCCAssignFn. NFC (#107503 )

2024-09-06 09:28:33 -07:00

RISCVCallingConv.td

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RISCVCodeGenPrepare.cpp

[RISCV] Use experimental.vp.splat to splat specific vector length elements. (#101329 )

2024-08-01 09:37:42 +08:00

RISCVCombine.td

[RISCV][GISEL] Introduce the RISCVPostLegalizerLowering pass (#108991 )

2024-09-17 13:18:35 -04:00

RISCVConstantPoolValue.cpp

[RISCV] Support the large code model. (#70308 )

2024-09-09 09:15:07 +08:00

RISCVConstantPoolValue.h

[RISCV] Support the large code model. (#70308 )

2024-09-09 09:15:07 +08:00

RISCVDeadRegisterDefinitions.cpp

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RISCVExpandAtomicPseudoInsts.cpp

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RISCVExpandPseudoInsts.cpp

[RISCV] Fix more boundary cases in immediate selection for Zdinx load/store on RV32. (#105874 )

2024-08-25 14:27:08 -07:00

RISCVFeatures.td

[RISCV] Remove unused HasStdExtB Predicate. NFC

2024-09-12 23:15:01 -07:00

RISCVFrameLowering.cpp

[RISCV][CFI] Emit cfi_offset for every callee-saved vector registers (#100455 )

2024-07-29 11:03:07 +08:00

RISCVFrameLowering.h

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RISCVGatherScatterLowering.cpp

Move stepvector intrinsic out of experimental namespace (#98043 )

2024-08-28 12:48:20 +01:00

RISCVGISel.td

[RISCV][GISel] Move i32 patterns that aren't used by SelectionDAG to RISCVGISel.td. NFC (#102685 )

2024-08-12 09:34:02 -07:00

RISCVIndirectBranchTracking.cpp

[RISCV] Insert simple landing pad before indirect jumps for Zicfilp. (#91860 )

2024-08-08 13:22:59 +08:00

RISCVInsertReadWriteCSR.cpp

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RISCVInsertVSETVLI.cpp

[RISCV] Rename merge operand -> passthru. NFC (#100330 )

2024-07-30 17:47:00 +08:00

RISCVInsertWriteVXRM.cpp

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RISCVInstrFormats.td

[RISCV] Model dest EEW and fix peepholes not checking EEW (#105945 )

2024-09-05 15:27:48 +08:00

RISCVInstrFormatsC.td

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RISCVInstrFormatsV.td

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RISCVInstrGISel.td

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RISCVInstrInfo.cpp

[RISCV] Don't outline pcrel_lo when the function has a section prefix (#107943 )

2024-09-11 09:53:11 -07:00

RISCVInstrInfo.h

[CodeGen] Add generic INIT_UNDEF pseudo (#106744 )

2024-09-05 09:34:39 +02:00

RISCVInstrInfo.td

[RISCV] Increase EmitPriority on some InstAliases. NFC

2024-09-12 19:33:59 -07:00

RISCVInstrInfoA.td

[RISCV][GISel] Move i32 patterns that aren't used by SelectionDAG to RISCVGISel.td. NFC (#102685 )

2024-08-12 09:34:02 -07:00

RISCVInstrInfoC.td

[RISCV] Fix InsnCI register type (#100113 )

2024-07-23 21:19:57 +08:00

RISCVInstrInfoD.td

[RISCV] Fix fneg.d/fabs.d aliasing handling for Zdinx. Add missing fmv.s/d aliases.

2024-09-10 11:44:04 -07:00

RISCVInstrInfoF.td

[RISCV] Enable floating point CSR alias mnemonics for Zfinx. (#108464 )

2024-09-12 18:40:52 -07:00

RISCVInstrInfoM.td

[RISCV][GISel] Move i32 patterns that aren't used by SelectionDAG to RISCVGISel.td. NFC (#102685 )

2024-08-12 09:34:02 -07:00

RISCVInstrInfoSFB.td

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RISCVInstrInfoV.td

[RISCV] Model dest EEW and fix peepholes not checking EEW (#105945 )

2024-09-05 15:27:48 +08:00

RISCVInstrInfoVPseudos.td

[RISCV] Generalize RISCVDAGToDAGISel::selectFPImm to handle bitcasts from int to FP. (#108284 )

2024-09-11 21:13:26 -07:00

RISCVInstrInfoVSDPatterns.td

[RISCV] Generalize RISCVDAGToDAGISel::selectFPImm to handle bitcasts from int to FP. (#108284 )

2024-09-11 21:13:26 -07:00

RISCVInstrInfoVVLPatterns.td

[RISCV] Generalize RISCVDAGToDAGISel::selectFPImm to handle bitcasts from int to FP. (#108284 )

2024-09-11 21:13:26 -07:00

RISCVInstrInfoXCV.td

[RISCV] Rename XCValu cv.slet(u) to cv.sle(u). (#108481 )

2024-09-12 21:39:01 -07:00

RISCVInstrInfoXSf.td

[RISCV] Model dest EEW and fix peepholes not checking EEW (#105945 )

2024-09-05 15:27:48 +08:00

RISCVInstrInfoXTHead.td

[RISCV] Separate ActiveElementsAffectResult into VL and Mask flags (#106517 )

2024-08-30 07:46:06 +08:00

RISCVInstrInfoXVentana.td

[RISCV] Remove IsRV64 from XVentanaCondOps patterns. (#100891 )

2024-07-27 17:26:32 -07:00

RISCVInstrInfoXwch.td

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RISCVInstrInfoZa.td

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RISCVInstrInfoZalasr.td

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RISCVInstrInfoZb.td

[RISCV] Improve BCLRITwoBitsMaskHigh SDNodeXForm. NFC

2024-08-19 10:32:47 -07:00

RISCVInstrInfoZc.td

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RISCVInstrInfoZcmop.td

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RISCVInstrInfoZfa.td

[RISCV] Expand Zfa fli+fneg cases during lowering instead of during isel. (#108316 )

2024-09-11 22:31:45 -07:00

RISCVInstrInfoZfbfmin.td

[RISCV] Remove RISCVISD::FP_ROUND_BF16.

2024-09-03 20:18:01 -07:00

RISCVInstrInfoZfh.td

[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138 )

2024-09-03 16:04:51 -07:00

RISCVInstrInfoZicbo.td

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RISCVInstrInfoZicfiss.td

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RISCVInstrInfoZicond.td

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RISCVInstrInfoZimop.td

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RISCVInstrInfoZk.td

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RISCVInstrInfoZvfbf.td

[RISCV] Model dest EEW and fix peepholes not checking EEW (#105945 )

2024-09-05 15:27:48 +08:00

RISCVInstrInfoZvk.td

[RISCV] Model dest EEW and fix peepholes not checking EEW (#105945 )

2024-09-05 15:27:48 +08:00

RISCVISelDAGToDAG.cpp

[RISCV] Expand Zfa fli+fneg cases during lowering instead of during isel. (#108316 )

2024-09-11 22:31:45 -07:00

RISCVISelDAGToDAG.h

[RISCV] Generalize RISCVDAGToDAGISel::selectFPImm to handle bitcasts from int to FP. (#108284 )

2024-09-11 21:13:26 -07:00

RISCVISelLowering.cpp

[RISCV] Remove unnecessary vand.vi from vXi1 and nvXvi1 VECTOR_REVERSE codegen. (#109071 )

2024-09-18 09:43:48 -07:00

RISCVISelLowering.h

[RISCV] Expand Zfa fli+fneg cases during lowering instead of during isel. (#108316 )

2024-09-11 22:31:45 -07:00

RISCVLandingPadSetup.cpp

[RISCV] Insert simple landing pad before indirect jumps for Zicfilp. (#91860 )

2024-08-08 13:22:59 +08:00

RISCVMachineFunctionInfo.cpp

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RISCVMachineFunctionInfo.h

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RISCVMacroFusion.td

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RISCVMakeCompressible.cpp

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RISCVMergeBaseOffset.cpp

[RISCV] Don't crash in RISCVMergeBaseOffset if INLINE_ASM uses address register in a non-memory constraint. (#100790 )

2024-07-26 17:11:01 -07:00

RISCVMoveMerger.cpp

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RISCVOptWInstrs.cpp

[RISCV] Add some Zfinx instructions to hasAllNBitUsers.

2024-08-08 17:33:54 -07:00

RISCVPostRAExpandPseudoInsts.cpp

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RISCVProcessors.td

[RISCV] Add scheduling model for Syntacore SCR7 (#108814 )

2024-09-17 18:52:55 +03:00

RISCVProfiles.td

[RISCV] Use listconcat to shorten some of the profile feature lists. (#102356 )

2024-08-08 09:15:43 -07:00

RISCVPushPopOptimizer.cpp

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RISCVRedundantCopyElimination.cpp

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RISCVRegisterInfo.cpp

[RISCV] Rename vcix_state register to sf_vcix_state. NFC (#106995 )

2024-09-03 15:55:39 +08:00

RISCVRegisterInfo.h

[InitUndef] Enable the InitUndef pass on non-AMDGPU targets (#108353 )

2024-09-16 09:48:25 +02:00

RISCVRegisterInfo.td

[RISCV] Rename sf_vcix_state to sf.vcix_state. NFC (#107115 )

2024-09-03 23:01:05 +08:00

RISCVSchedRocket.td

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RISCVSchedSiFive7.td

[RISCV][SiFive7] Change Latency of VCIX to the default (#106497 )

2024-09-05 13:01:29 -04:00

RISCVSchedSiFiveP400.td

[RISCV] Add vector and vector crypto to SiFiveP400 scheduler model (#102155 )

2024-08-19 09:41:42 -04:00

RISCVSchedSiFiveP600.td

[RISCV] Rename merge operand -> passthru. NFC (#100330 )

2024-07-30 17:47:00 +08:00

RISCVSchedSyntacoreSCR1.td

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RISCVSchedSyntacoreSCR7.td

[RISCV] Add scheduling model for Syntacore SCR7 (#108814 )

2024-09-17 18:52:55 +03:00

RISCVSchedSyntacoreSCR345.td

[RISCV] Add scheduling model for Syntacore SCR4 and SCR5 (#102909 )

2024-08-14 11:42:31 +03:00

RISCVSchedule.td

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RISCVScheduleV.td

[RISCV] Move VLDSX0Pred from RISCVSchedSiFive7.td to RISCVScheduleV.td. NFC (#106671 )

2024-09-01 21:02:06 -07:00

RISCVScheduleXSf.td

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RISCVScheduleZb.td

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RISCVScheduleZvk.td

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RISCVSchedXiangShanNanHu.td

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RISCVSubtarget.cpp

[RISCV] Disable fixed length vectors with Zve32* without Zvl64b. (#102405 )

2024-08-08 09:17:43 -07:00

RISCVSubtarget.h

[InitUndef] Enable the InitUndef pass on non-AMDGPU targets (#108353 )

2024-09-16 09:48:25 +02:00

RISCVSystemOperands.td

[RISCV] Add CSRs and an instruction for Smctr and Ssctr extensions. (#105148 )

2024-08-21 19:23:07 -07:00

RISCVTargetMachine.cpp

[RISCV][GISEL] Introduce the RISCVPostLegalizerLowering pass (#108991 )

2024-09-17 13:18:35 -04:00

RISCVTargetMachine.h

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RISCVTargetObjectFile.cpp

[RISCV] Support the large code model. (#70308 )

2024-09-09 09:15:07 +08:00

RISCVTargetObjectFile.h

[Driver] Default -msmall-data-limit= to 0 and clean up code

2024-08-19 18:20:02 -07:00

RISCVTargetTransformInfo.cpp

[RISCV][TTI] Adjust cost for extract/insert element when VLEN is known (#108595 )

2024-09-17 08:43:40 -07:00

RISCVTargetTransformInfo.h

[RISCV][TTI] Add legality check of vector of address for gather/scatter. (#106481 )

2024-08-30 10:50:15 +08:00

RISCVVectorPeephole.cpp

[RISCV] Add reductions to list of roots in tryToReduceVL (#107595 )

2024-09-10 18:47:20 -07:00