Vyacheslav Levytskyy 08f5f6dc8b [SPIR-V] Fix incorrect emission of G_SPLAT_VECTOR for fixed vectors (#108534) ...

This PR replaces MIRBuilder.buildSplatVector() by
MIRBuilder.buildSplatBuildVector(), so that we emit G_BUILD_VECTOR
instead of G_SPLAT_VECTOR: the latter is incorrect for fixed vectors and
is limited to scalable vectors only.

2024-09-18 09:22:30 +02:00

..

Analysis

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MCTargetDesc

[SPIR-V] Rework usage of virtual registers' types and classes (#104104)

2024-08-22 09:40:27 +02:00

TargetInfo

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CMakeLists.txt

[SPIR-V] Expose an API call to initialize SPIRV target and translate input LLVM IR module to SPIR-V (#107216)

2024-09-10 15:51:20 +02:00

SPIRV.h

[SPIRV] Emitting DebugSource, DebugCompileUnit (#97558)

2024-08-22 20:27:36 -07:00

SPIRV.td

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SPIRVAPI.cpp

[SPIR-V] Expose an API call to initialize SPIRV target and translate input LLVM IR module to SPIR-V (#107216)

2024-09-10 15:51:20 +02:00

SPIRVAPI.h

[SPIR-V] Expose an API call to initialize SPIRV target and translate input LLVM IR module to SPIR-V (#107216)

2024-09-10 15:51:20 +02:00

SPIRVAsmPrinter.cpp

[SPIRV] Emitting DebugSource, DebugCompileUnit (#97558)

2024-08-22 20:27:36 -07:00

SPIRVBuiltins.cpp

[SPIR-V] Rework usage of virtual registers' types and classes (#104104)

2024-08-22 09:40:27 +02:00

SPIRVBuiltins.h

[SPIRV] Improve type inference of operand presented by opaque pointers and aggregate types (#98035)

2024-07-11 07:16:29 +02:00

SPIRVBuiltins.td

[SPIR-V] Fix vload_half builtin argument count (#105585)

2024-08-27 01:26:26 -07:00

SPIRVCallLowering.cpp

[SPIR-V] Rework usage of virtual registers' types and classes (#104104)

2024-08-22 09:40:27 +02:00

SPIRVCallLowering.h

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SPIRVCommandLine.cpp

[SPIR-V] Expose an API call to initialize SPIRV target and translate input LLVM IR module to SPIR-V (#107216)

2024-09-10 15:51:20 +02:00

SPIRVCommandLine.h

[SPIR-V] Expose an API call to initialize SPIRV target and translate input LLVM IR module to SPIR-V (#107216)

2024-09-10 15:51:20 +02:00

SPIRVDuplicatesTracker.cpp

[SPIR-V] Address the case when optimization uses GEP operator and GenCode creates G_PTR_ADD to convey the semantics (#107880)

2024-09-11 14:18:14 +02:00

SPIRVDuplicatesTracker.h

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SPIRVEmitIntrinsics.cpp

[SPIRV] Fix build after change in transitive includes (#106140)

2024-08-26 14:01:15 -07:00

SPIRVEmitNonSemanticDI.cpp

[SPIR-V] Emit DebugTypeBasic for NonSemantic DI (#106980)

2024-09-16 18:26:22 -07:00

SPIRVFrameLowering.h

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SPIRVGlobalRegistry.cpp

[SPIR-V] Fix incorrect emission of G_SPLAT_VECTOR for fixed vectors (#108534)

2024-09-18 09:22:30 +02:00

SPIRVGlobalRegistry.h

[SPIR-V] Rework usage of virtual registers' types and classes (#104104)

2024-08-22 09:40:27 +02:00

SPIRVInlineAsmLowering.cpp

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SPIRVInlineAsmLowering.h

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SPIRVInstrFormats.td

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SPIRVInstrInfo.cpp

[TII][RISCV] Add renamable bit to copyPhysReg (#91179)

2024-08-27 10:08:43 +08:00

SPIRVInstrInfo.h

[TII][RISCV] Add renamable bit to copyPhysReg (#91179)

2024-08-27 10:08:43 +08:00

SPIRVInstrInfo.td

[SPIR-V] Improve correctness of emitted MIR between passes for branching instructions (#106966)

2024-09-03 19:02:03 +02:00

SPIRVInstructionSelector.cpp

Add step builtins and step HLSL function to DirectX and SPIR-V backend (#106471)

2024-09-12 10:26:38 -07:00

SPIRVISelLowering.cpp

[SPIR-V] Improve correctness of emitted MIR between passes for branching instructions (#106966)

2024-09-03 19:02:03 +02:00

SPIRVISelLowering.h

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SPIRVLegalizerInfo.cpp

[SPIR-V] Rework usage of virtual registers' types and classes (#104104)

2024-08-22 09:40:27 +02:00

SPIRVLegalizerInfo.h

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SPIRVMCInstLower.cpp

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SPIRVMCInstLower.h

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SPIRVMergeRegionExitTargets.cpp

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SPIRVMetadata.cpp

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SPIRVMetadata.h

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SPIRVModuleAnalysis.cpp

[SPIR-V] Emit DebugTypeBasic for NonSemantic DI (#106980)

2024-09-16 18:26:22 -07:00

SPIRVModuleAnalysis.h

[SPIRV] Emitting DebugSource, DebugCompileUnit (#97558)

2024-08-22 20:27:36 -07:00

SPIRVPostLegalizer.cpp

[SPIR-V] Rework usage of virtual registers' types and classes (#104104)

2024-08-22 09:40:27 +02:00

SPIRVPreLegalizer.cpp

[SPIR-V] Improve correctness of emitted MIR between passes for branching instructions (#106966)

2024-09-03 19:02:03 +02:00

SPIRVPrepareFunctions.cpp

[SPIRV] Improve type inference of operand presented by opaque pointers and aggregate types (#98035)

2024-07-11 07:16:29 +02:00

SPIRVRegisterBankInfo.cpp

[GISel][TableGen] Generate getRegBankFromRegClass (#99896)

2024-07-25 09:41:55 -04:00

SPIRVRegisterBankInfo.h

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SPIRVRegisterBanks.td

[SPIR-V] Rework usage of virtual registers' types and classes (#101732)

2024-08-12 15:49:43 +02:00

SPIRVRegisterInfo.cpp

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SPIRVRegisterInfo.h

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SPIRVRegisterInfo.td

[SPIR-V] Rework usage of virtual registers' types and classes (#104104)

2024-08-22 09:40:27 +02:00

SPIRVRegularizer.cpp

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SPIRVStripConvergentIntrinsics.cpp

[clang][HLSL] Add WaveIsFirstLane() intrinsic (#103299)

2024-09-04 11:27:03 +02:00

SPIRVSubtarget.cpp

[SPIR-V] Expose an API call to initialize SPIRV target and translate input LLVM IR module to SPIR-V (#107216)

2024-09-10 15:51:20 +02:00

SPIRVSubtarget.h

[SPIR-V] Expose an API call to initialize SPIRV target and translate input LLVM IR module to SPIR-V (#107216)

2024-09-10 15:51:20 +02:00

SPIRVSymbolicOperands.td

[SPIR-V] Address the case when optimization uses GEP operator and GenCode creates G_PTR_ADD to convey the semantics (#107880)

2024-09-11 14:18:14 +02:00

SPIRVTargetMachine.cpp

[ExtendLifetimes] Implement llvm.fake.use to extend variable lifetimes (#86149)

2024-08-29 17:53:32 +01:00

SPIRVTargetMachine.h

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SPIRVTargetObjectFile.h

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SPIRVTargetTransformInfo.h

[IR] Add getDataLayout() helpers to Function and GlobalValue (#96919)

2024-06-28 08:36:49 +02:00

SPIRVUtils.cpp

[SPIR-V]: Fix creation of constants of array types in SPIRV Backend (#96514)

2024-06-25 10:56:56 +02:00

SPIRVUtils.h

[SPIRV] Improve type inference of operand presented by opaque pointers and aggregate types (#98035)

2024-07-11 07:16:29 +02:00