Shih-Po Hung ffcff2f465 [VPlan][NFC] Fix the value name of VECTOR_GEP (#107544) ...

This patch passes the string `"vector.gep"` to CreateGEP instead of
CreateMul.

2024-09-18 19:22:36 +08:00

..

blocks-with-dead-instructions.ll

[VPlan] Add VPValue for VF, use it for VPWidenIntOrFpInductionRecipe. (#95305)

2024-09-10 10:41:35 +01:00

dead-ops-cost.ll

[LV] Assign cost to all interleave members when not interleaving.

2024-09-11 21:04:34 +01:00

defaults.ll

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divrem.ll

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evl-compatible-loops.ll

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first-order-recurrence-scalable-vf1.ll

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force-vect-msg.ll

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illegal-type.ll

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induction-costs.ll

[VPlan] Add VPValue for VF, use it for VPWidenIntOrFpInductionRecipe. (#95305)

2024-09-10 10:41:35 +01:00

inloop-reduction.ll

[LV] Support binary and unary operations with EVL-vectorization (#93854)

2024-09-06 11:41:36 -04:00

interleaved-accesses-zve32x.ll

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interleaved-accesses.ll

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interleaved-cost.ll

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lit.local.cfg

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lmul.ll

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low-trip-count.ll

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mask-index-type.ll

[VPlan] Add VPValue for VF, use it for VPWidenIntOrFpInductionRecipe. (#95305)

2024-09-10 10:41:35 +01:00

masked_gather_scatter.ll

[VPlan] Add VPValue for VF, use it for VPWidenIntOrFpInductionRecipe. (#95305)

2024-09-10 10:41:35 +01:00

only-compute-cost-for-vplan-vfs.ll

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ordered-reduction.ll

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pr87378-vpinstruction-or-drop-poison-generating-flags.ll

[VPlan] Add VPValue for VF, use it for VPWidenIntOrFpInductionRecipe. (#95305)

2024-09-10 10:41:35 +01:00

pr88802.ll

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reg-usage-bf16.ll

[RISCV] Add asserts requirement to loop vectorizer tests

2024-09-17 14:18:36 +08:00

reg-usage-f16.ll

[RISCV] Add asserts requirement to loop vectorizer tests

2024-09-17 14:18:36 +08:00

reg-usage.ll

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riscv-interleaved.ll

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riscv-unroll.ll

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riscv-vector-reverse.ll

[VPlan] Add VPIRInstruction, use for exit block live-outs. (#100735)

2024-09-14 21:21:55 +01:00

safe-dep-distance.ll

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scalable-basics.ll

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scalable-reductions.ll

Prefer use of 0.0 over -0.0 for fadd reductions w/nsz (in IR) (#106770)

2024-09-03 09:16:37 -07:00

scalable-tailfold.ll

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scalable-vf-hint.ll

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select-cmp-reduction.ll

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short-trip-count.ll

[RISCV][TTI] Properly model odd vector sized LD/ST operations (#100436)

2024-07-26 12:52:20 -07:00

strided-accesses.ll

[VPlan][NFC] Fix the value name of VECTOR_GEP (#107544)

2024-09-18 19:22:36 +08:00

truncate-to-minimal-bitwidth-cost.ll

[LV] Remove over-aggressive assert from 3fe6a064f1.

2024-09-05 18:20:16 +01:00

uniform-load-store.ll

[VPlan] Add VPValue for VF, use it for VPWidenIntOrFpInductionRecipe. (#95305)

2024-09-10 10:41:35 +01:00

unroll-in-loop-vectorizer.ll

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vectorize-force-tail-with-evl-bin-unary-ops-args.ll

[LV] Support binary and unary operations with EVL-vectorization (#93854)

2024-09-06 11:41:36 -04:00

vectorize-force-tail-with-evl-cond-reduction.ll

[VPlan] Add VPValue for VF, use it for VPWidenIntOrFpInductionRecipe. (#95305)

2024-09-10 10:41:35 +01:00

vectorize-force-tail-with-evl-gather-scatter.ll

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vectorize-force-tail-with-evl-inloop-reduction.ll

[LV] Prefer FLT_MIN/MAX for fmin/fmax reductions with ninf (#107141)

2024-09-03 12:21:54 -07:00

vectorize-force-tail-with-evl-interleave.ll

[VPlan] Add VPValue for VF, use it for VPWidenIntOrFpInductionRecipe. (#95305)

2024-09-10 10:41:35 +01:00

vectorize-force-tail-with-evl-intermediate-store.ll

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vectorize-force-tail-with-evl-iv32.ll

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vectorize-force-tail-with-evl-masked-loadstore.ll

[LV] Support binary and unary operations with EVL-vectorization (#93854)

2024-09-06 11:41:36 -04:00

vectorize-force-tail-with-evl-no-masking.ll

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vectorize-force-tail-with-evl-ordered-reduction.ll

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vectorize-force-tail-with-evl-reduction.ll

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vectorize-force-tail-with-evl-reverse-load-store.ll

[LV] Support binary and unary operations with EVL-vectorization (#93854)

2024-09-06 11:41:36 -04:00

vectorize-force-tail-with-evl-safe-dep-distance.ll

[LV][VP][NFC]Add tests for safe store/load forwarding/dependence distance.

2024-07-25 19:55:37 -04:00

vectorize-vp-intrinsics.ll

[LV] Support binary and unary operations with EVL-vectorization (#93854)

2024-09-06 11:41:36 -04:00

vf-will-not-generate-any-vector-insts.ll

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vplan-vp-intrinsics-reduction.ll

[VPlan] Add VPIRInstruction, use for exit block live-outs. (#100735)

2024-09-14 21:21:55 +01:00

vplan-vp-intrinsics.ll

[LV][NFC] Unify printing for WidenEVLReicpe with other EVL recipes (#108177)

2024-09-18 15:03:37 +08:00

zvl32b.ll

[RISCV] Disable fixed length vectors with Zve32* without Zvl64b. (#102405)

2024-08-08 09:17:43 -07:00