ca6a890d7f
For the hard float calling convention, we just use the D registers. For the soft-fp calling convention, we use the R registers and move values to/from the D registers by means of G_SEQUENCE/G_EXTRACT. While doing so, we make sure to honor the endianness of the target, since the CCAssignFn doesn't do that for us. For pure soft float targets, we still bail out because we don't support the libcalls yet. llvm-svn: 295295
307 lines
11 KiB
C++
307 lines
11 KiB
C++
//===-- llvm/lib/Target/ARM/ARMCallLowering.cpp - Call lowering -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file implements the lowering of LLVM calls to machine code calls for
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/// GlobalISel.
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///
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//===----------------------------------------------------------------------===//
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#include "ARMCallLowering.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMISelLowering.h"
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#include "ARMSubtarget.h"
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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#ifndef LLVM_BUILD_GLOBAL_ISEL
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#error "This shouldn't be built without GISel"
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#endif
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ARMCallLowering::ARMCallLowering(const ARMTargetLowering &TLI)
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: CallLowering(&TLI) {}
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static bool isSupportedType(const DataLayout &DL, const ARMTargetLowering &TLI,
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Type *T) {
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EVT VT = TLI.getValueType(DL, T, true);
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if (!VT.isSimple() || VT.isVector())
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return false;
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unsigned VTSize = VT.getSimpleVT().getSizeInBits();
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if (VTSize == 64)
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// FIXME: Support i64 too
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return VT.isFloatingPoint();
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return VTSize == 1 || VTSize == 8 || VTSize == 16 || VTSize == 32;
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}
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namespace {
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struct FuncReturnHandler : public CallLowering::ValueHandler {
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FuncReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
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MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
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: ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
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unsigned getStackAddress(uint64_t Size, int64_t Offset,
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MachinePointerInfo &MPO) override {
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llvm_unreachable("Don't know how to get a stack address yet");
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}
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void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
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CCValAssign &VA) override {
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assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
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assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
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assert(VA.getValVT().getSizeInBits() <= 64 && "Unsupported value size");
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assert(VA.getLocVT().getSizeInBits() <= 64 && "Unsupported location size");
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unsigned ExtReg = extendRegister(ValVReg, VA);
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MIRBuilder.buildCopy(PhysReg, ExtReg);
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MIB.addUse(PhysReg, RegState::Implicit);
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}
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void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
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MachinePointerInfo &MPO, CCValAssign &VA) override {
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llvm_unreachable("Don't know how to assign a value to an address yet");
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}
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unsigned assignCustomValue(const CallLowering::ArgInfo &Arg,
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ArrayRef<CCValAssign> VAs) override {
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CCValAssign VA = VAs[0];
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assert(VA.needsCustom() && "Value doesn't need custom handling");
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assert(VA.getValVT() == MVT::f64 && "Unsupported type");
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CCValAssign NextVA = VAs[1];
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assert(NextVA.needsCustom() && "Value doesn't need custom handling");
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assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
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assert(VA.getValNo() == NextVA.getValNo() &&
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"Values belong to different arguments");
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assert(VA.isRegLoc() && "Value should be in reg");
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assert(NextVA.isRegLoc() && "Value should be in reg");
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unsigned NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
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MRI.createGenericVirtualRegister(LLT::scalar(32))};
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MIRBuilder.buildExtract(NewRegs, {0, 32}, Arg.Reg);
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bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
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if (!IsLittle)
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std::swap(NewRegs[0], NewRegs[1]);
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assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
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assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
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return 1;
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}
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MachineInstrBuilder &MIB;
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};
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} // End anonymous namespace.
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void ARMCallLowering::splitToValueTypes(const ArgInfo &OrigArg,
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SmallVectorImpl<ArgInfo> &SplitArgs,
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const DataLayout &DL,
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MachineRegisterInfo &MRI) const {
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const ARMTargetLowering &TLI = *getTLI<ARMTargetLowering>();
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LLVMContext &Ctx = OrigArg.Ty->getContext();
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SmallVector<EVT, 4> SplitVTs;
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SmallVector<uint64_t, 4> Offsets;
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ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0);
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assert(SplitVTs.size() == 1 && "Unsupported type");
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// Even if there is no splitting to do, we still want to replace the original
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// type (e.g. pointer type -> integer).
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SplitArgs.emplace_back(OrigArg.Reg, SplitVTs[0].getTypeForEVT(Ctx),
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OrigArg.Flags, OrigArg.IsFixed);
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}
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/// Lower the return value for the already existing \p Ret. This assumes that
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/// \p MIRBuilder's insertion point is correct.
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bool ARMCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
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const Value *Val, unsigned VReg,
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MachineInstrBuilder &Ret) const {
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if (!Val)
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// Nothing to do here.
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return true;
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auto &MF = MIRBuilder.getMF();
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const auto &F = *MF.getFunction();
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auto DL = MF.getDataLayout();
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auto &TLI = *getTLI<ARMTargetLowering>();
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if (!isSupportedType(DL, TLI, Val->getType()))
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return false;
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SmallVector<ArgInfo, 4> SplitVTs;
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ArgInfo RetInfo(VReg, Val->getType());
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setArgFlags(RetInfo, AttributeSet::ReturnIndex, DL, F);
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splitToValueTypes(RetInfo, SplitVTs, DL, MF.getRegInfo());
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CCAssignFn *AssignFn =
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TLI.CCAssignFnForReturn(F.getCallingConv(), F.isVarArg());
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FuncReturnHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret, AssignFn);
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return handleAssignments(MIRBuilder, SplitVTs, RetHandler);
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}
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bool ARMCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
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const Value *Val, unsigned VReg) const {
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assert(!Val == !VReg && "Return value without a vreg");
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auto Ret = MIRBuilder.buildInstrNoInsert(ARM::BX_RET).add(predOps(ARMCC::AL));
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if (!lowerReturnVal(MIRBuilder, Val, VReg, Ret))
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return false;
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MIRBuilder.insertInstr(Ret);
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return true;
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}
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namespace {
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struct FormalArgHandler : public CallLowering::ValueHandler {
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FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
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CCAssignFn AssignFn)
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: ValueHandler(MIRBuilder, MRI, AssignFn) {}
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unsigned getStackAddress(uint64_t Size, int64_t Offset,
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MachinePointerInfo &MPO) override {
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assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
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"Unsupported size");
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auto &MFI = MIRBuilder.getMF().getFrameInfo();
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int FI = MFI.CreateFixedObject(Size, Offset, true);
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MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
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unsigned AddrReg =
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MRI.createGenericVirtualRegister(LLT::pointer(MPO.getAddrSpace(), 32));
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MIRBuilder.buildFrameIndex(AddrReg, FI);
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return AddrReg;
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}
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void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
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MachinePointerInfo &MPO, CCValAssign &VA) override {
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assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
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"Unsupported size");
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if (VA.getLocInfo() == CCValAssign::SExt ||
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VA.getLocInfo() == CCValAssign::ZExt) {
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// If the argument is zero- or sign-extended by the caller, its size
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// becomes 4 bytes, so that's what we should load.
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Size = 4;
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assert(MRI.getType(ValVReg).isScalar() && "Only scalars supported atm");
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MRI.setType(ValVReg, LLT::scalar(32));
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}
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auto MMO = MIRBuilder.getMF().getMachineMemOperand(
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MPO, MachineMemOperand::MOLoad, Size, /* Alignment */ 0);
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MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
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}
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void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
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CCValAssign &VA) override {
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assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
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assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
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assert(VA.getValVT().getSizeInBits() <= 64 && "Unsupported value size");
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assert(VA.getLocVT().getSizeInBits() <= 64 && "Unsupported location size");
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// The caller should handle all necesary extensions.
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MIRBuilder.getMBB().addLiveIn(PhysReg);
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MIRBuilder.buildCopy(ValVReg, PhysReg);
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}
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unsigned assignCustomValue(const llvm::ARMCallLowering::ArgInfo &Arg,
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ArrayRef<CCValAssign> VAs) override {
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CCValAssign VA = VAs[0];
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assert(VA.needsCustom() && "Value doesn't need custom handling");
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assert(VA.getValVT() == MVT::f64 && "Unsupported type");
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CCValAssign NextVA = VAs[1];
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assert(NextVA.needsCustom() && "Value doesn't need custom handling");
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assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
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assert(VA.getValNo() == NextVA.getValNo() &&
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"Values belong to different arguments");
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assert(VA.isRegLoc() && "Value should be in reg");
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assert(NextVA.isRegLoc() && "Value should be in reg");
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unsigned NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
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MRI.createGenericVirtualRegister(LLT::scalar(32))};
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assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
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assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
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bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
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if (!IsLittle)
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std::swap(NewRegs[0], NewRegs[1]);
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MIRBuilder.buildSequence(Arg.Reg, NewRegs, {0, 32});
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return 1;
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}
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};
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} // End anonymous namespace
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bool ARMCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
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const Function &F,
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ArrayRef<unsigned> VRegs) const {
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// Quick exit if there aren't any args
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if (F.arg_empty())
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return true;
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if (F.isVarArg())
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return false;
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auto &MF = MIRBuilder.getMF();
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auto DL = MF.getDataLayout();
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auto &TLI = *getTLI<ARMTargetLowering>();
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auto Subtarget = TLI.getSubtarget();
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if (Subtarget->isThumb())
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return false;
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// FIXME: Support soft float (when we're ready to generate libcalls)
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if (Subtarget->useSoftFloat() || !Subtarget->hasVFP2())
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return false;
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auto &Args = F.getArgumentList();
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for (auto &Arg : Args)
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if (!isSupportedType(DL, TLI, Arg.getType()))
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return false;
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CCAssignFn *AssignFn =
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TLI.CCAssignFnForCall(F.getCallingConv(), F.isVarArg());
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SmallVector<ArgInfo, 8> ArgInfos;
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unsigned Idx = 0;
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for (auto &Arg : Args) {
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ArgInfo AInfo(VRegs[Idx], Arg.getType());
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setArgFlags(AInfo, Idx + 1, DL, F);
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splitToValueTypes(AInfo, ArgInfos, DL, MF.getRegInfo());
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Idx++;
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}
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FormalArgHandler ArgHandler(MIRBuilder, MIRBuilder.getMF().getRegInfo(),
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AssignFn);
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return handleAssignments(MIRBuilder, ArgInfos, ArgHandler);
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}
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