60e6ce4155
Summary: The fX version of floating-point registers only supports single precision. We need to map the name to dX for doubles and qX for long doubles if we want getRegForInlineAsmConstraint() to be able to pick the correct register class. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D47258 llvm-svn: 333512
133 lines
4.1 KiB
LLVM
133 lines
4.1 KiB
LLVM
; RUN: llc -march=sparc <%s | FileCheck %s
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; CHECK-LABEL: test_constraint_r
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; CHECK: add %o1, %o0, %o0
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define i32 @test_constraint_r(i32 %a, i32 %b) {
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entry:
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%0 = tail call i32 asm sideeffect "add $2, $1, $0", "=r,r,r"(i32 %a, i32 %b)
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ret i32 %0
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}
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;; Check tests only that the constraints are accepted without a compiler failure.
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; CHECK-LABEL: test_constraints_nro:
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%struct.anon = type { i32, i32 }
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@v = external global %struct.anon, align 4
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define void @test_constraints_nro() {
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entry:
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%0 = load i32, i32* getelementptr inbounds (%struct.anon, %struct.anon* @v, i32 0, i32 0);
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%1 = load i32, i32* getelementptr inbounds (%struct.anon, %struct.anon* @v, i32 0, i32 1);
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tail call void asm sideeffect "", "nro,nro"(i32 %0, i32 %1)
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ret void
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}
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; CHECK-LABEL: test_constraint_I:
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; CHECK: add %o0, 1023, %o0
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define i32 @test_constraint_I(i32 %a) {
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entry:
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%0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 1023)
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ret i32 %0
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}
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; CHECK-LABEL: test_constraint_I_neg:
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; CHECK: add %o0, -4096, %o0
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define i32 @test_constraint_I_neg(i32 %a) {
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entry:
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%0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 -4096)
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ret i32 %0
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}
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; CHECK-LABEL: test_constraint_I_largeimm:
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; CHECK: sethi 9, [[R0:%[gilo][0-7]]]
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; CHECK: or [[R0]], 784, [[R1:%[gilo][0-7]]]
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; CHECK: add %o0, [[R1]], %o0
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define i32 @test_constraint_I_largeimm(i32 %a) {
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entry:
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%0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 10000)
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ret i32 %0
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}
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; CHECK-LABEL: test_constraint_reg:
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; CHECK: ldda [%o1] 43, %g2
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; CHECK: ldda [%o1] 43, %g4
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define void @test_constraint_reg(i32 %s, i32* %ptr) {
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entry:
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%0 = tail call i64 asm sideeffect "ldda [$1] $2, $0", "={r2},r,n"(i32* %ptr, i32 43)
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%1 = tail call i64 asm sideeffect "ldda [$1] $2, $0", "={g4},r,n"(i32* %ptr, i32 43)
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ret void
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}
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;; Ensure that i64 args to asm are allocated to the IntPair register class.
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;; Also checks that register renaming for leaf proc works.
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; CHECK-LABEL: test_constraint_r_i64:
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; CHECK: mov %o0, %o5
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; CHECK: sra %o5, 31, %o4
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; CHECK: std %o4, [%o1]
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define i32 @test_constraint_r_i64(i32 %foo, i64* %out, i32 %o) {
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entry:
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%conv = sext i32 %foo to i64
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tail call void asm sideeffect "std $0, [$1]", "r,r,~{memory}"(i64 %conv, i64* %out)
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ret i32 %o
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}
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;; Same test without leaf-proc opt
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; CHECK-LABEL: test_constraint_r_i64_noleaf:
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; CHECK: mov %i0, %i5
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; CHECK: sra %i5, 31, %i4
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; CHECK: std %i4, [%i1]
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define i32 @test_constraint_r_i64_noleaf(i32 %foo, i64* %out, i32 %o) #0 {
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entry:
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%conv = sext i32 %foo to i64
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tail call void asm sideeffect "std $0, [$1]", "r,r,~{memory}"(i64 %conv, i64* %out)
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ret i32 %o
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}
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attributes #0 = { "no-frame-pointer-elim"="true" }
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;; Ensures that tied in and out gets allocated properly.
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; CHECK-LABEL: test_i64_inout:
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; CHECK: mov %g0, %o2
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; CHECK: mov 5, %o3
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; CHECK: xor %o2, %g0, %o2
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; CHECK: mov %o2, %o0
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; CHECK: ret
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define i64 @test_i64_inout() {
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entry:
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%0 = call i64 asm sideeffect "xor $1, %g0, $0", "=r,0,~{i1}"(i64 5);
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ret i64 %0
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}
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;; Ensures that inline-asm accepts and uses 'f' and 'e' register constraints.
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; CHECK-LABEL: fadds:
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; CHECK: fadds %f0, %f1, %f0
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define float @fadds(float, float) local_unnamed_addr #2 {
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entry:
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%2 = tail call float asm sideeffect "fadds $1, $2, $0;", "=f,f,e"(float %0, float %1) #7
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ret float %2
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}
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; CHECK-LABEL: faddd:
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; CHECK: faddd %f0, %f2, %f0
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define double @faddd(double, double) local_unnamed_addr #2 {
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entry:
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%2 = tail call double asm sideeffect "faddd $1, $2, $0;", "=f,f,e"(double %0, double %1) #7
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ret double %2
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}
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; CHECK-LABEL: test_addressing_mode_i64:
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; CHECK: std %l0, [%o0]
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define void @test_addressing_mode_i64(i64* %out) {
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entry:
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call void asm "std %l0, $0", "=*m,r"(i64* nonnull %out, i64 0)
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ret void
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}
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; CHECK-LABEL: test_constraint_float_reg:
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; CHECK: fadds %f20, %f20, %f20
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; CHECK: faddd %f20, %f20, %f20
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define void @test_constraint_float_reg() {
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entry:
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tail call void asm sideeffect "fadds $0,$1,$2", "{f20},{f20},{f20}"(float 6.0, float 7.0, float 8.0)
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tail call void asm sideeffect "faddd $0,$1,$2", "{f20},{f20},{f20}"(double 9.0, double 10.0, double 11.0)
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ret void
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}
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