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clang-p2996/llvm/lib/Target/RISCV
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eopXD b089e4072a [RISCV] Don't allow i64 vector div by constant to use mulh with Zve64x 
EEW=64 of mulh and its vairants requires V extension.

Authored by: Craig Topper <craig.topper@sifive.com> @craig.topper

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D117947
2022-01-25 09:55:05 -08:00
..
AsmParser
[RISCV] Initially support the K-extension instructions on the LLVM MC layer
2022-01-24 14:45:35 +08:00
Disassembler
…
MCTargetDesc
[RISCV] Initially support the K-extension instructions on the LLVM MC layer
2022-01-24 14:45:35 +08:00
TargetInfo
…
CMakeLists.txt
[RISCV] Add an MIR pass to replace redundant sext.w instructions with copies.
2022-01-06 08:23:42 -08:00
RISCV.h
[RISCV] Add an MIR pass to replace redundant sext.w instructions with copies.
2022-01-06 08:23:42 -08:00
RISCV.td
[RISCV] add support for zbkx subextension in MC layer.
2022-01-24 20:38:46 +08:00
RISCVAsmPrinter.cpp
…
RISCVCallingConv.td
…
RISCVCallLowering.cpp
…
RISCVCallLowering.h
…
RISCVExpandAtomicPseudoInsts.cpp
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RISCVExpandPseudoInsts.cpp
…
RISCVFrameLowering.cpp
[RISCV] Fix the bug in the register allocator caused by reserved BP.
2022-01-21 01:23:01 +00:00
RISCVFrameLowering.h
…
RISCVGatherScatterLowering.cpp
[RISCV] Teach RISCVGatherScatterLowering to handle more complex recurrence start values.
2022-01-04 10:13:34 -08:00
RISCVInsertVSETVLI.cpp
[RISCV] Prune unnecessary vector pseudo instructions. NFC
2022-01-01 19:53:53 -08:00
RISCVInstrFormats.td
[RISCV] Add strictfp support for compares.
2022-01-11 20:01:41 -08:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
[RISCV] Remove Zvamo Extention
2021-12-20 10:28:39 +08:00
RISCVInstrInfo.cpp
[RISCV] Add missing space to 'clang-format on' directive. NFC
2022-01-24 17:00:37 -08:00
RISCVInstrInfo.h
[RISCV] Use AdjustInstrPostInstrSelection to insert a FRM dependency for scalar FP instructions with dynamic rounding mode.
2021-12-14 10:17:57 -08:00
RISCVInstrInfo.td
[RISCV] Initially support the K-extension instructions on the LLVM MC layer
2022-01-24 14:45:35 +08:00
RISCVInstrInfoA.td
…
RISCVInstrInfoC.td
[llvm-tblgen][RISCV] Make llvm-tblgen RISCVCompressInstEmitter to be common infra across different targets
2021-11-18 11:14:27 +08:00
RISCVInstrInfoD.td
[RISCV] Optimize lowering of floating-point -0.0
2022-01-20 11:46:28 +00:00
RISCVInstrInfoF.td
[RISCV] Optimize lowering of floating-point -0.0
2022-01-20 11:46:28 +00:00
RISCVInstrInfoM.td
[RISCV] Use MULHU for more division by constant cases.
2021-12-09 09:10:14 -08:00
RISCVInstrInfoV.td
[RISCV] Remove Zvlsseg extension.
2022-01-20 12:40:07 -08:00
RISCVInstrInfoVPseudos.td
[RISCV] Select int_riscv_vsll with shift of 1 to vadd.vv.
2022-01-24 08:04:53 -08:00
RISCVInstrInfoVSDPatterns.td
[RISCV][NFC] Remove tailing whitespaces in RISCVInstrInfoVSDPatterns.td and RISCVInstrInfoVVLPatterns.td
2022-01-24 10:49:43 +08:00
RISCVInstrInfoVVLPatterns.td
[RISCV][VP] Lower VP_MERGE to RVV instructions
2022-01-24 11:05:05 +00:00
RISCVInstrInfoZb.td
[RISCV] add support for zbkx subextension in MC layer.
2022-01-24 20:38:46 +08:00
RISCVInstrInfoZfh.td
[RISCV] Optimize lowering of floating-point -0.0
2022-01-20 11:46:28 +00:00
RISCVInstrInfoZk.td
[RISCV] Initially support the K-extension instructions on the LLVM MC layer
2022-01-24 14:45:35 +08:00
RISCVInstructionSelector.cpp
[Target] Remove redundant member initialization (NFC)
2022-01-06 22:01:44 -08:00
RISCVISelDAGToDAG.cpp
[RISCV] Add side-effect-free vsetvli intrinsics
2022-01-24 13:52:08 +00:00
RISCVISelDAGToDAG.h
[RISCV] Add side-effect-free vsetvli intrinsics
2022-01-24 13:52:08 +00:00
RISCVISelLowering.cpp
[RISCV] Don't allow i64 vector div by constant to use mulh with Zve64x
2022-01-25 09:55:05 -08:00
RISCVISelLowering.h
[RISCV][VP] Lower VP_MERGE to RVV instructions
2022-01-24 11:05:05 +00:00
RISCVLegalizerInfo.cpp
…
RISCVLegalizerInfo.h
…
RISCVMachineFunctionInfo.h
…
RISCVMCInstLower.cpp
[NFC] Use Register instead of unsigned
2022-01-19 20:17:04 +08:00
RISCVMergeBaseOffset.cpp
…
RISCVRegisterBankInfo.cpp
Revert "[llvm] Remove redundant member initialization (NFC)"
2022-01-03 11:28:47 -08:00
RISCVRegisterBankInfo.h
…
RISCVRegisterBanks.td
…
RISCVRegisterInfo.cpp
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
RISCVRegisterInfo.h
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
RISCVRegisterInfo.td
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
RISCVSchedRocket.td
[RISCV] add support for zbkx subextension in MC layer.
2022-01-24 20:38:46 +08:00
RISCVSchedSiFive7.td
[RISCV] add support for zbkx subextension in MC layer.
2022-01-24 20:38:46 +08:00
RISCVSchedule.td
…
RISCVScheduleB.td
[RISCV] Add instruction schedule for Zbc extension and Zbs extension
2022-01-18 07:31:50 +00:00
RISCVScheduleV.td
…
RISCVSExtWRemoval.cpp
[RISCV] Add patterns to MIR sign-extension removal pass.
2022-01-19 17:33:58 -08:00
RISCVSubtarget.cpp
[RISCV] Factor Zve32 support into RISCVSubtarget::getMaxELENForFixedLengthVectors.
2022-01-20 16:31:12 -08:00
RISCVSubtarget.h
[RISCV] Don't allow i64 vector div by constant to use mulh with Zve64x
2022-01-25 09:55:05 -08:00
RISCVSystemOperands.td
[RISCV] Initially support the K-extension instructions on the LLVM MC layer
2022-01-24 14:45:35 +08:00
RISCVTargetMachine.cpp
[RISCV] Add an MIR pass to replace redundant sext.w instructions with copies.
2022-01-06 08:23:42 -08:00
RISCVTargetMachine.h
…
RISCVTargetObjectFile.cpp
…
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[RISCV] Add initial support for getRegUsageForType and getNumberOfRegisters
2022-01-17 15:27:54 +08:00
RISCVTargetTransformInfo.h
[RISCV] Add initial support for getRegUsageForType and getNumberOfRegisters
2022-01-17 15:27:54 +08:00