Aart Bik 92c1c63dae [mlir][sparse] integration test for sparse output operation ...

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D118079

2022-01-24 17:41:09 -08:00

..

Async/CPU

[mlir] AsyncParallelFor: align block size to be a multiple of inner loops iterations

2021-12-09 06:50:50 -08:00

Linalg/CPU

[mlir] Move linalg::PadTensorOp to tensor::PadOp.

2022-01-21 20:02:39 +01:00

LLVMIR/CPU

[mlir][Vector] Add a vblendps-based impl for transpose8x8 (both intrin and inline_asm)

2021-11-23 07:31:22 +00:00

Memref

Add an example of integration test invoking MLIR source with Memref from C

2022-01-12 20:18:56 +00:00

PDL/CPU

[MLIR][PDL] Integration test of multi-root matching and related fixes.

2022-01-04 08:03:45 +05:30

SparseTensor

[mlir][sparse] integration test for sparse output operation

2022-01-24 17:41:09 -08:00

Standard/CPU

[mlir][MemRef] Deprecate unspecified trailing offset, size, and strides semantics of OffsetSizeAndStrideOpInterface.

2021-12-29 11:18:29 -08:00

Vector/CPU

[mlir][vector] Allow values outside of [0; dim-size] in create_mask

2022-01-20 09:34:42 -08:00