Chuanqi Xu dbbe010908 [MLIR] [AsyncToLLVM] Use llvm.coro.align intrinsic ...

Use llvm.coro.align to align coroutine frame properly.

Reviewed By: bkramer

Differential Revision: https://reviews.llvm.org/D117978

2022-01-25 19:28:25 +08:00

..

amx.mlir

[mlir][amx] Add Intel AMX dialect (architectural-specific vector dialect)

2021-03-15 17:59:05 -07:00

arm-neon-2d.mlir

2d Arm Neon sdot op, and lowering to the intrinsic.

2021-06-10 14:36:39 -07:00

arm-neon.mlir

Fix some typos.

2021-05-14 21:34:09 +05:30

arm-sve.mlir

[mlir][RFC] Add scalable dimensions to VectorType

2021-12-15 09:31:37 +00:00

import.ll

[mlir] Support alignment in LLVM dialect GlobalOp

2021-05-12 09:07:20 +02:00

llvmir-debug.mlir

…

llvmir-intrinsics.mlir

[MLIR] [AsyncToLLVM] Use llvm.coro.align intrinsic

2022-01-25 19:28:25 +08:00

llvmir-invalid.mlir

[mlir] support translating OpenMP loops with reductions

2021-09-02 15:38:20 +02:00

llvmir-types.mlir

[mlir] Fix scalable type translation in splat element attr

2022-01-13 11:14:41 +00:00

llvmir.mlir

[mlir] Fix invalid assertion in ModuleTranslation.cpp

2022-01-14 12:56:33 +01:00

nvvmir.mlir

[mlir] Replace StrEnumAttr -> EnumAttr in core dialects

2022-01-18 17:15:00 +00:00

openacc-llvm.mlir

[OpenMP][OpenACC] Update test after encoding change in D113126

2021-12-29 01:29:07 -06:00

openmp-llvm-bad-schedule-modifier.mlir

[mlir][OpenMP] Add support for SIMD modifier

2021-11-26 14:04:46 +00:00

openmp-llvm.mlir

[MLIR][OpenMP] Support schedule chunk size with various bit width

2022-01-19 12:36:53 +08:00

openmp-reduction.mlir

[mlir] support translating OpenMP loops with reductions

2021-09-02 15:38:20 +02:00

rocdl.mlir

[MLIR][GPU] Make max flat work group size for ROCDL kernels configurable

2021-12-14 20:12:23 +00:00

vector-to-llvm-ir.mlir

[MLIR] Replace std ops with arith dialect ops

2021-10-13 03:07:03 +00:00

x86vector.mlir

[mlir] X86Vector: Add AVX Rsqrt

2021-04-13 08:43:48 -07:00