4f672a34ed
Summary: The goal is for each operand type to have its own parse function and at the same time share common code for tracking state as different instruction types share operand types (e.g. glc/glc_flat, etc). Introduce parseAMDGPUOperand which can parse any optional operand. DPP and Clamp/OMod have custom handling for now. Sam also suggested to have class hierarchy for operand types instead of table. This can be done in separate change. Remove parseVOP3OptionalOps, parseDS*OptionalOps, parseFlatOptionalOps, parseMubufOptionalOps, parseDPPOptionalOps. Reduce number of definitions of AsmOperand's and MatchClasses' by using common base class. Rename AsmMatcher/InstPrinter methods accordingly. Print immediate type when printing parsed immediate operand. Use 'off' if offset/index register is unused instead of skipping it to make it more readable (also agreed with SP3). Update tests. Reviewers: tstellarAMD, SamWot, artem.tamazov Subscribers: qcolombet, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19584 llvm-svn: 268015
184 lines
8.0 KiB
LLVM
184 lines
8.0 KiB
LLVM
; RUN: llc -march=amdgcn -show-mc-encoding -verify-machineinstrs < %s | FileCheck %s
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declare i32 @llvm.amdgcn.workitem.id.x() readnone
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;;;==========================================================================;;;
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;;; MUBUF LOAD TESTS
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;;;==========================================================================;;;
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; MUBUF load with an immediate byte offset that fits into 12-bits
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; CHECK-LABEL: {{^}}mubuf_load0:
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; CHECK: buffer_load_dword v{{[0-9]}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:4 ; encoding: [0x04,0x00,0x30,0xe0
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define void @mubuf_load0(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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entry:
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%0 = getelementptr i32, i32 addrspace(1)* %in, i64 1
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%1 = load i32, i32 addrspace(1)* %0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; MUBUF load with the largest possible immediate offset
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; CHECK-LABEL: {{^}}mubuf_load1:
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; CHECK: buffer_load_ubyte v{{[0-9]}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe0
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define void @mubuf_load1(i8 addrspace(1)* %out, i8 addrspace(1)* %in) {
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entry:
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%0 = getelementptr i8, i8 addrspace(1)* %in, i64 4095
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%1 = load i8, i8 addrspace(1)* %0
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store i8 %1, i8 addrspace(1)* %out
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ret void
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}
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; MUBUF load with an immediate byte offset that doesn't fit into 12-bits
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; CHECK-LABEL: {{^}}mubuf_load2:
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; CHECK: s_movk_i32 [[SOFFSET:s[0-9]+]], 0x1000
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; CHECK: buffer_load_dword v{{[0-9]}}, off, s[{{[0-9]+:[0-9]+}}], [[SOFFSET]] ; encoding: [0x00,0x00,0x30,0xe0
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define void @mubuf_load2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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entry:
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%0 = getelementptr i32, i32 addrspace(1)* %in, i64 1024
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%1 = load i32, i32 addrspace(1)* %0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; MUBUF load with a 12-bit immediate offset and a register offset
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; CHECK-LABEL: {{^}}mubuf_load3:
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; CHECK-NOT: ADD
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; CHECK: buffer_load_dword v{{[0-9]}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:4 ; encoding: [0x04,0x80,0x30,0xe0
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define void @mubuf_load3(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i64 %offset) {
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entry:
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%0 = getelementptr i32, i32 addrspace(1)* %in, i64 %offset
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%1 = getelementptr i32, i32 addrspace(1)* %0, i64 1
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%2 = load i32, i32 addrspace(1)* %1
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store i32 %2, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}soffset_max_imm:
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; CHECK: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 64 offen glc
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define amdgpu_gs void @soffset_max_imm([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) {
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main_body:
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%tmp0 = getelementptr [6 x <16 x i8>], [6 x <16 x i8>] addrspace(2)* %0, i32 0, i32 0
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%tmp1 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp0
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%tmp2 = shl i32 %6, 2
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%tmp3 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %tmp1, i32 %tmp2, i32 64, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0)
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%tmp4 = add i32 %6, 16
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%tmp5 = bitcast float 0.0 to i32
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call void @llvm.SI.tbuffer.store.i32(<16 x i8> %tmp1, i32 %tmp5, i32 1, i32 %tmp4, i32 %4, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
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ret void
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}
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; Make sure immediates that aren't inline constants don't get folded into
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; the soffset operand.
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; FIXME: for this test we should be smart enough to shift the immediate into
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; the offset field.
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; CHECK-LABEL: {{^}}soffset_no_fold:
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; CHECK: s_movk_i32 [[SOFFSET:s[0-9]+]], 0x41
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; CHECK: buffer_load_dword v{{[0-9+]}}, v{{[0-9+]}}, s[{{[0-9]+}}:{{[0-9]+}}], [[SOFFSET]] offen glc
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define amdgpu_gs void @soffset_no_fold([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) {
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main_body:
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%tmp0 = getelementptr [6 x <16 x i8>], [6 x <16 x i8>] addrspace(2)* %0, i32 0, i32 0
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%tmp1 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp0
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%tmp2 = shl i32 %6, 2
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%tmp3 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %tmp1, i32 %tmp2, i32 65, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0)
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%tmp4 = add i32 %6, 16
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%tmp5 = bitcast float 0.0 to i32
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call void @llvm.SI.tbuffer.store.i32(<16 x i8> %tmp1, i32 %tmp5, i32 1, i32 %tmp4, i32 %4, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
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ret void
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}
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;;;==========================================================================;;;
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;;; MUBUF STORE TESTS
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;;;==========================================================================;;;
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; MUBUF store with an immediate byte offset that fits into 12-bits
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; CHECK-LABEL: {{^}}mubuf_store0:
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; CHECK: buffer_store_dword v{{[0-9]}}, off, s[{{[0-9]:[0-9]}}], 0 offset:4 ; encoding: [0x04,0x00,0x70,0xe0
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define void @mubuf_store0(i32 addrspace(1)* %out) {
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entry:
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%0 = getelementptr i32, i32 addrspace(1)* %out, i64 1
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store i32 0, i32 addrspace(1)* %0
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ret void
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}
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; MUBUF store with the largest possible immediate offset
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; CHECK-LABEL: {{^}}mubuf_store1:
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; CHECK: buffer_store_byte v{{[0-9]}}, off, s[{{[0-9]:[0-9]}}], 0 offset:4095 ; encoding: [0xff,0x0f,0x60,0xe0
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define void @mubuf_store1(i8 addrspace(1)* %out) {
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entry:
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%0 = getelementptr i8, i8 addrspace(1)* %out, i64 4095
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store i8 0, i8 addrspace(1)* %0
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ret void
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}
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; MUBUF store with an immediate byte offset that doesn't fit into 12-bits
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; CHECK-LABEL: {{^}}mubuf_store2:
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; CHECK: s_movk_i32 [[SOFFSET:s[0-9]+]], 0x1000
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; CHECK: buffer_store_dword v{{[0-9]}}, off, s[{{[0-9]:[0-9]}}], [[SOFFSET]] ; encoding: [0x00,0x00,0x70,0xe0
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define void @mubuf_store2(i32 addrspace(1)* %out) {
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entry:
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%0 = getelementptr i32, i32 addrspace(1)* %out, i64 1024
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store i32 0, i32 addrspace(1)* %0
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ret void
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}
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; MUBUF store with a 12-bit immediate offset and a register offset
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; CHECK-LABEL: {{^}}mubuf_store3:
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; CHECK-NOT: ADD
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; CHECK: buffer_store_dword v{{[0-9]}}, v[{{[0-9]:[0-9]}}], s[{{[0-9]:[0-9]}}], 0 addr64 offset:4 ; encoding: [0x04,0x80,0x70,0xe0
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define void @mubuf_store3(i32 addrspace(1)* %out, i64 %offset) {
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entry:
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%0 = getelementptr i32, i32 addrspace(1)* %out, i64 %offset
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%1 = getelementptr i32, i32 addrspace(1)* %0, i64 1
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store i32 0, i32 addrspace(1)* %1
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ret void
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}
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; CHECK-LABEL: {{^}}store_sgpr_ptr:
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; CHECK: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0
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define void @store_sgpr_ptr(i32 addrspace(1)* %out) #0 {
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store i32 99, i32 addrspace(1)* %out, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}store_sgpr_ptr_offset:
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; CHECK: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:40
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define void @store_sgpr_ptr_offset(i32 addrspace(1)* %out) #0 {
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%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 10
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store i32 99, i32 addrspace(1)* %out.gep, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}store_sgpr_ptr_large_offset:
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; CHECK: s_mov_b32 [[SOFFSET:s[0-9]+]], 0x20000
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; CHECK: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, [[SOFFSET]]
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define void @store_sgpr_ptr_large_offset(i32 addrspace(1)* %out) #0 {
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%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 32768
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store i32 99, i32 addrspace(1)* %out.gep, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}store_sgpr_ptr_large_offset_atomic:
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; CHECK: s_mov_b32 [[SOFFSET:s[0-9]+]], 0x20000
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; CHECK: buffer_atomic_add v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, [[SOFFSET]]
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define void @store_sgpr_ptr_large_offset_atomic(i32 addrspace(1)* %out) #0 {
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%gep = getelementptr i32, i32 addrspace(1)* %out, i32 32768
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%val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 5 seq_cst
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ret void
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}
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; CHECK-LABEL: {{^}}store_vgpr_ptr:
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; CHECK: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64
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define void @store_vgpr_ptr(i32 addrspace(1)* %out) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() readnone
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%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
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store i32 99, i32 addrspace(1)* %out.gep, align 4
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ret void
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}
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declare i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #3
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declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)
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attributes #1 = { "unsafe-fp-math"="true" }
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attributes #3 = { nounwind readonly }
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