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e62c54375d2e75acaaa1394de99f4f61462e7530
clang-p2996/llvm/test/Transforms/LoopVectorize/AArch64
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James Molloy aa1d638800 Revert "[VectorUtils] Query number of sign bits to allow more truncations"
This was a fairly simple patch but on closer inspection was seriously flawed and caused PR27690.

This reverts commit r268921.

llvm-svn: 269051
2016-05-10 12:27:23 +00:00
..
aarch64-unroll.ll
…
arbitrary-induction-step.ll
…
arm64-unroll.ll
…
backedge-overflow.ll
Re-commit [SCEV] Introduce a guarded backedge taken count and use it in LAA and LV
2016-04-08 14:29:09 +00:00
deterministic-type-shrinkage.ll
[LoopVectorize] Use MapVector rather than DenseMap for MinBWs.
2015-11-26 20:39:51 +00:00
first-order-recurrence.ll
[LoopUtils, LV] Fix PR27246 (first-order recurrences)
2016-04-11 19:48:18 +00:00
gather-cost.ll
…
interleaved_cost.ll
…
lit.local.cfg
…
loop-vectorization-factors.ll
Revert "[VectorUtils] Query number of sign bits to allow more truncations"
2016-05-10 12:27:23 +00:00
reduction-small-size.ll
[LV] Relax Small Size Reduction Type Requirement
2015-09-10 21:12:57 +00:00
sdiv-pow2.ll
…
type-shrinkage-insertelt.ll
[LV] Add support for insertelt/extractelt processing during type truncation
2016-02-15 15:38:17 +00:00
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