caio/clang-p2996
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
ea2c159f966be363d5c19df8d116d471604f7db5
clang-p2996/llvm/lib/Target/AMDGPU
History
Simon Pilgrim ea2c159f96 [AMDGPU] Fix "use of uninitialized variable" static analyzer warning. NFCI. 
Add "unreachable" default case to AMDGPUTargetStreamer::getArchNameFromElfMach
2020-01-06 16:36:56 +00:00
..
AsmParser
[APFloat] Add recoverable string parsing errors to APFloat
2020-01-06 10:09:01 +02:00
Disassembler
[AMDGPU][MC] Remove duplicate code introduced in r359316.
2019-12-04 11:44:12 +00:00
MCTargetDesc
[AMDGPU] Fix "use of uninitialized variable" static analyzer warning. NFCI.
2020-01-06 16:36:56 +00:00
TargetInfo
[cmake] Explicitly mark libraries defined in lib/ as "Component Libraries"
2019-11-21 10:48:08 -08:00
Utils
[IR] Split out target specific intrinsic enums into separate headers
2019-12-11 18:02:14 -08:00
AMDGPU.h
[IR] Split out target specific intrinsic enums into separate headers
2019-12-11 18:02:14 -08:00
AMDGPU.td
[AMDGPU] w/a for gfx908 mfma SrcC literal HW bug
2019-08-23 22:09:58 +00:00
AMDGPUAliasAnalysis.cpp
AMDGPU: Improve alias analysis for GDS
2019-07-17 11:22:19 +00:00
AMDGPUAliasAnalysis.h
…
AMDGPUAlwaysInlinePass.cpp
AMDGPU: Simplify getAddressSpace calls
2019-10-31 07:51:38 -07:00
AMDGPUAnnotateKernelFeatures.cpp
Use llvm::StringLiteral instead of StringRef in few places
2019-09-20 14:31:42 +00:00
AMDGPUAnnotateUniformValues.cpp
Sink all InitializePasses.h includes
2019-11-13 16:34:37 -08:00
AMDGPUArgumentUsageInfo.cpp
[AMDGPU] Packed thread ids in function call ABI
2019-06-28 01:52:13 +00:00
AMDGPUArgumentUsageInfo.h
AMDGPU: Fix Register copypaste error
2019-09-05 23:07:10 +00:00
AMDGPUAsmPrinter.cpp
[NFC] Fix trivial typos in comments
2020-01-06 10:50:26 +00:00
AMDGPUAsmPrinter.h
[AMDGPU] separate accounting for agprs
2019-10-02 00:26:58 +00:00
AMDGPUAtomicOptimizer.cpp
Sink all InitializePasses.h includes
2019-11-13 16:34:37 -08:00
AMDGPUCallingConv.td
[AMDGPU] Adjust number of SGPRs available in Calling Convention
2019-08-28 15:00:45 +00:00
AMDGPUCallLowering.cpp
[AMDGPU] Don't create MachinePointerInfos with an UndefValue pointer
2019-12-23 15:58:19 +00:00
AMDGPUCallLowering.h
AMDGPU/GlobalISel: Rename MIRBuilder to B. NFC
2019-09-09 23:06:13 +00:00
AMDGPUCodeGenPrepare.cpp
AMDGPU: Refactor treatment of denormal mode
2019-11-19 19:55:43 +05:30
AMDGPUFeatures.td
…
AMDGPUFixFunctionBitcasts.cpp
…
AMDGPUFrameLowering.cpp
Use Align for TFL::TransientStackAlignment
2019-10-21 08:31:25 +00:00
AMDGPUFrameLowering.h
Use Align for TFL::TransientStackAlignment
2019-10-21 08:31:25 +00:00
AMDGPUGenRegisterBankInfo.def
AMDGPU/GlobalISel: Add AGPR bank and RegBankSelect mfma intrinsics
2019-12-01 22:15:48 -08:00
AMDGPUGISel.td
AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG
2019-10-25 13:11:09 -07:00
AMDGPUGlobalISelUtils.cpp
AMDGPU/GlobalISel: Add new utils file
2020-01-03 15:25:50 -05:00
AMDGPUGlobalISelUtils.h
AMDGPU/GlobalISel: Add new utils file
2020-01-03 15:25:50 -05:00
AMDGPUHSAMetadataStreamer.cpp
[AMDGPU] add support for hostcall buffer pointer as hidden kernel argument
2019-11-20 15:53:55 +05:30
AMDGPUHSAMetadataStreamer.h
[llvm] Migrate llvm::make_unique to std::make_unique
2019-08-15 15:54:37 +00:00
AMDGPUInline.cpp
[AMDGPU] Tune inlining parameters for AMDGPU target (part 2)
2019-11-19 16:33:16 +03:00
AMDGPUInstrInfo.cpp
…
AMDGPUInstrInfo.h
…
AMDGPUInstrInfo.td
AMDGPU/GlobalISel: Select mul24 intrinsics
2019-12-30 14:24:25 -05:00
AMDGPUInstructions.td
AMDGPU/GlobalISel: Select scalar v2s16 G_BUILD_VECTOR
2020-01-06 11:19:33 -05:00
AMDGPUInstructionSelector.cpp
AMDGPU/GlobalISel: Select scalar v2s16 G_BUILD_VECTOR
2020-01-06 11:19:33 -05:00
AMDGPUInstructionSelector.h
GlobalISel: Lower s1 source G_SITOFP/G_UITOFP
2019-11-15 13:37:20 +05:30
AMDGPUISelDAGToDAG.cpp
AMDGPU: Refactor treatment of denormal mode
2019-11-19 19:55:43 +05:30
AMDGPUISelLowering.cpp
[TargetLowering][AMDGPU] Make scalarizeVectorLoad return a pair of SDValues instead of creating a MERGE_VALUES node. NFCI
2019-12-30 19:36:04 -08:00
AMDGPUISelLowering.h
AMDGPU: Improve llvm.round.f64 lowering for CI+
2019-12-30 09:55:46 -05:00
AMDGPULegalizerInfo.cpp
GlobalISel: Scalarize all division operations
2020-01-04 13:47:10 -05:00
AMDGPULegalizerInfo.h
AMDGPU/GlobalISel: Legalize FDIV64
2019-11-19 21:02:27 -08:00
AMDGPULibCalls.cpp
Sink all InitializePasses.h includes
2019-11-13 16:34:37 -08:00
AMDGPULibFunc.cpp
[AMDGPU] Downgrade from StringLiteral to const char* in an attempt to make GCC 5 happy
2019-08-25 12:47:31 +00:00
AMDGPULibFunc.h
…
AMDGPULowerIntrinsics.cpp
…
AMDGPULowerKernelArguments.cpp
[Alignment] Migrate Attribute::getWith(Stack)Alignment
2019-10-15 12:56:24 +00:00
AMDGPULowerKernelAttributes.cpp
…
AMDGPUMachineCFGStructurizer.cpp
[AMDGPU] Fixes -Wrange-loop-analysis warnings
2019-12-22 19:39:28 +01:00
AMDGPUMachineFunction.cpp
AMDGPU: Refactor treatment of denormal mode
2019-11-19 19:55:43 +05:30
AMDGPUMachineFunction.h
AMDGPU: Refactor treatment of denormal mode
2019-11-19 19:55:43 +05:30
AMDGPUMachineModuleInfo.cpp
…
AMDGPUMachineModuleInfo.h
…
AMDGPUMacroFusion.cpp
…
AMDGPUMacroFusion.h
…
AMDGPUMCInstLower.cpp
[AMDGPU] link dpp pseudos and real instructions on gfx10
2019-10-11 22:03:36 +00:00
AMDGPUOpenCLEnqueuedBlockLowering.cpp
Fix parameter name comments using clang-tidy. NFC.
2019-07-16 04:46:31 +00:00
AMDGPUPerfHintAnalysis.cpp
AMDGPU: Fix assert in clang test
2019-07-05 21:09:53 +00:00
AMDGPUPerfHintAnalysis.h
AMDGPU: Make AMDGPUPerfHintAnalysis an SCC pass
2019-07-05 20:26:13 +00:00
AMDGPUPrintfRuntimeBinding.cpp
[AMDGPU] add support for hostcall buffer pointer as hidden kernel argument
2019-11-20 15:53:55 +05:30
AMDGPUPromoteAlloca.cpp
Resubmit "[Alignment][NFC] Deprecate CreateMemCpy/CreateMemMove"
2019-12-17 10:07:46 +01:00
AMDGPUPropagateAttributes.cpp
AMDGPU: Move DEBUG_TYPE definition below includes
2019-07-08 18:48:39 +00:00
AMDGPUPTNote.h
…
AMDGPURegisterBankInfo.cpp
AMDGPU/GlobalISel: Refine SMRD selection rules
2020-01-04 12:40:35 -05:00
AMDGPURegisterBankInfo.h
GlobalISel: Add type argument to getRegBankFromRegClass
2020-01-03 16:25:10 -05:00
AMDGPURegisterBanks.td
AMDGPU/GlobalISel: Add AGPR bank and RegBankSelect mfma intrinsics
2019-12-01 22:15:48 -08:00
AMDGPURegisterInfo.cpp
AMDGPU/GlobalISel: Handle more G_INSERT cases
2019-10-07 19:16:26 +00:00
AMDGPURegisterInfo.h
AMDGPU/GlobalISel: Handle more G_INSERT cases
2019-10-07 19:16:26 +00:00
AMDGPURegisterInfo.td
[AMDGPU] gfx908 register file changes
2019-07-09 19:41:51 +00:00
AMDGPURewriteOutArguments.cpp
Sink all InitializePasses.h includes
2019-11-13 16:34:37 -08:00
AMDGPUSearchableTables.td
[AMDGPU][SILoadStoreOptimizer] Merge TBUFFER loads/stores
2019-11-20 22:59:30 +01:00
AMDGPUSubtarget.cpp
AMDGPU: Switch backend default max workgroup size to 1024
2019-11-13 07:11:02 +05:30
AMDGPUSubtarget.h
AMDGPU: Refactor treatment of denormal mode
2019-11-19 19:55:43 +05:30
AMDGPUTargetMachine.cpp
Sink all InitializePasses.h includes
2019-11-13 16:34:37 -08:00
AMDGPUTargetMachine.h
…
AMDGPUTargetObjectFile.cpp
…
AMDGPUTargetObjectFile.h
…
AMDGPUTargetTransformInfo.cpp
[AMDGPU] Implemented fma cost analysis
2019-12-18 23:54:20 -08:00
AMDGPUTargetTransformInfo.h
[AMDGPU] Implemented fma cost analysis
2019-12-18 23:54:20 -08:00
AMDGPUUnifyDivergentExitNodes.cpp
Sink all InitializePasses.h includes
2019-11-13 16:34:37 -08:00
AMDGPUUnifyMetadata.cpp
[AMDGPU] Fixes -Wrange-loop-analysis warnings
2019-12-22 19:39:28 +01:00
AMDILCFGStructurizer.cpp
Sink all InitializePasses.h includes
2019-11-13 16:34:37 -08:00
AMDKernelCodeT.h
[AMDGPU] gfx1010 wave32 metadata
2019-06-17 16:48:56 +00:00
BUFInstructions.td
[AMDGPU] drop getIsFP td helper
2019-10-17 21:46:56 +00:00
CaymanInstructions.td
…
CMakeLists.txt
AMDGPU/GlobalISel: Add new utils file
2020-01-03 15:25:50 -05:00
DSInstructions.td
[AMDGPU] Add missing flags to DS_Real
2019-11-05 14:24:48 -08:00
EvergreenInstructions.td
AMDGPU: Start redefining atomic PatFrags
2019-08-01 03:25:52 +00:00
FLATInstructions.td
AMDGPU/GlobalISel: Select some 128-bit load/stores
2019-12-27 08:49:43 -05:00
GCNDPPCombine.cpp
[AMDGPU][DPP] Corrected DPP combiner
2019-11-20 15:56:45 +03:00
GCNHazardRecognizer.cpp
Make more use of MachineInstr::mayLoadOrStore.
2019-12-19 11:51:52 +00:00
GCNHazardRecognizer.h
[AMDGPU] gfx908 hazard recognizer
2019-07-11 21:30:34 +00:00
GCNILPSched.cpp
Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each
2019-10-19 01:31:09 +00:00
GCNIterativeScheduler.cpp
[llvm] Migrate llvm::make_unique to std::make_unique
2019-08-15 15:54:37 +00:00
GCNIterativeScheduler.h
…
GCNMinRegStrategy.cpp
…
GCNNSAReassign.cpp
Sink all InitializePasses.h includes
2019-11-13 16:34:37 -08:00
GCNProcessors.td
[AMDGPU] gfx908 target
2019-07-09 18:10:06 +00:00
GCNRegBankReassign.cpp
Sink all InitializePasses.h includes
2019-11-13 16:34:37 -08:00
GCNRegPressure.cpp
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
2019-08-15 19:22:08 +00:00
GCNRegPressure.h
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC
2019-08-01 23:27:28 +00:00
GCNSchedStrategy.cpp
[AMDGPU] Revert scheduling to reduce spilling
2020-01-03 15:20:21 -08:00
GCNSchedStrategy.h
AMDGPU: Avoid constructing new std::vector in initCandidate
2019-09-05 22:44:06 +00:00
LLVMBuild.txt
…
MIMGInstructions.td
[AMDGPU] deduplicate tablegen predicates
2019-11-04 12:19:17 -08:00
R600.td
…
R600AsmPrinter.cpp
[NFC] Fix trivial typos in comments
2020-01-06 10:50:26 +00:00
R600AsmPrinter.h
…
R600ClauseMergePass.cpp
…
R600ControlFlowFinalizer.cpp
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
2019-08-15 19:22:08 +00:00
R600Defines.h
…
R600EmitClauseMarkers.cpp
…
R600ExpandSpecialInstrs.cpp
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
2019-08-15 19:22:08 +00:00
R600FrameLowering.cpp
…
R600FrameLowering.h
Use Align for TFL::TransientStackAlignment
2019-10-21 08:31:25 +00:00
R600InstrFormats.td
…
R600InstrInfo.cpp
Use MCRegister in copyPhysReg
2019-11-11 14:42:33 +05:30
R600InstrInfo.h
Use MCRegister in copyPhysReg
2019-11-11 14:42:33 +05:30
R600Instructions.td
AMDGPU: Redefine load PatFrags
2019-07-16 17:38:50 +00:00
R600ISelLowering.cpp
[TargetLowering][AMDGPU] Make scalarizeVectorLoad return a pair of SDValues instead of creating a MERGE_VALUES node. NFCI
2019-12-30 19:36:04 -08:00
R600ISelLowering.h
…
R600MachineFunctionInfo.cpp
…
R600MachineFunctionInfo.h
…
R600MachineScheduler.cpp
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
2019-08-15 19:22:08 +00:00
R600MachineScheduler.h
…
R600OpenCLImageTypeLoweringPass.cpp
…
R600OptimizeVectorRegisters.cpp
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
2019-08-15 19:22:08 +00:00
R600Packetizer.cpp
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
2019-08-15 19:22:08 +00:00
R600Processors.td
…
R600RegisterInfo.cpp
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC
2019-08-01 23:27:28 +00:00
R600RegisterInfo.h
CodeGen: Introduce a class for registers
2019-06-24 15:50:29 +00:00
R600RegisterInfo.td
…
R600Schedule.td
…
R700Instructions.td
…
SIAddIMGInit.cpp
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
2019-08-15 19:22:08 +00:00
SIAnnotateControlFlow.cpp
Sink all InitializePasses.h includes
2019-11-13 16:34:37 -08:00
SIDefines.h
[AMDGPU] Added MI bit IsDOT
2019-09-17 17:56:13 +00:00
SIFixSGPRCopies.cpp
Sink all InitializePasses.h includes
2019-11-13 16:34:37 -08:00
SIFixupVectorISel.cpp
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC
2019-08-01 23:27:28 +00:00
SIFixVGPRCopies.cpp
…
SIFoldOperands.cpp
AMDGPU: Avoid folding 2 constant operands into an SALU operation
2019-12-04 10:25:34 +00:00
SIFormMemoryClauses.cpp
Sink all InitializePasses.h includes
2019-11-13 16:34:37 -08:00
SIFrameLowering.cpp
[AMDGPU] Don't create MachinePointerInfos with an UndefValue pointer
2019-12-23 15:58:19 +00:00
SIFrameLowering.h
Use Align for TFL::TransientStackAlignment
2019-10-21 08:31:25 +00:00
SIInsertSkips.cpp
[AMDGPU] gfx10 conditional registers handling
2019-06-16 17:13:09 +00:00
SIInsertWaitcnts.cpp
[AMDGPU] need to insert wait between the scalar load and vector store to the same address to avoid WAR conflict.
2020-01-04 18:23:14 +03:00
SIInstrFormats.td
[AMDGPU] Added MI bit IsDOT
2019-09-17 17:56:13 +00:00
SIInstrInfo.cpp
TII: Fix using Register for a subregister index argument
2019-12-27 16:53:29 -05:00
SIInstrInfo.h
TII: Fix using Register for a subregister index argument
2019-12-27 16:53:29 -05:00
SIInstrInfo.td
AMDGPU: Select global atomicrmw fadd
2019-11-06 16:06:38 -08:00
SIInstructions.td
AMDGPU/GlobalISel: Select scalar v2s16 G_BUILD_VECTOR
2020-01-06 11:19:33 -05:00
SIISelLowering.cpp
[amdgpu] Skip non-instruction values in CF user tracing.
2020-01-03 16:02:47 -05:00
SIISelLowering.h
AMDGPU: Refactor treatment of denormal mode
2019-11-19 19:55:43 +05:30
SILoadStoreOptimizer.cpp
AMDGPU/SILoadStoreOptimillzer: Refactor CombineInfo struct
2019-12-17 13:43:10 -08:00
SILowerControlFlow.cpp
[AMDGPU] Fix emitIfBreak CF lowering: use temp reg to make register coalescer life easier.
2019-11-26 18:59:37 +03:00
SILowerI1Copies.cpp
Sink all InitializePasses.h includes
2019-11-13 16:34:37 -08:00
SILowerSGPRSpills.cpp
Sink all InitializePasses.h includes
2019-11-13 16:34:37 -08:00
SIMachineFunctionInfo.cpp
AMDGPU: Refactor treatment of denormal mode
2019-11-19 19:55:43 +05:30
SIMachineFunctionInfo.h
AMDGPU: Refactor treatment of denormal mode
2019-11-19 19:55:43 +05:30
SIMachineScheduler.cpp
AMDGPU/SI: make ~SIScheduleBlockCreator trivial
2019-11-11 21:51:59 -08:00
SIMachineScheduler.h
AMDGPU/SI: make ~SIScheduleBlockCreator trivial
2019-11-11 21:51:59 -08:00
SIMemoryLegalizer.cpp
[llvm] Migrate llvm::make_unique to std::make_unique
2019-08-15 15:54:37 +00:00
SIModeRegister.cpp
[llvm] Migrate llvm::make_unique to std::make_unique
2019-08-15 15:54:37 +00:00
SIOptimizeExecMasking.cpp
AMDGPU: Use Register
2019-12-27 16:53:21 -05:00
SIOptimizeExecMaskingPreRA.cpp
Sink all InitializePasses.h includes
2019-11-13 16:34:37 -08:00
SIPeepholeSDWA.cpp
AMDGPU: Fixed indeterminate map iteration in SIPeepholeSDWA
2019-12-02 12:08:49 +00:00
SIPreAllocateWWMRegs.cpp
Sink all InitializePasses.h includes
2019-11-13 16:34:37 -08:00
SIProgramInfo.h
[AMDGPU] separate accounting for agprs
2019-10-02 00:26:58 +00:00
SIRegisterInfo.cpp
Fix broken comment phrasing and indentation
2019-12-02 12:23:20 +05:30
SIRegisterInfo.h
AMDGPU/GlobalISel: Add AGPR bank and RegBankSelect mfma intrinsics
2019-12-01 22:15:48 -08:00
SIRegisterInfo.td
AMDGPU: Make VReg_1 only include 1 artificial register
2019-10-28 20:51:51 -07:00
SISchedule.td
[AMDGPU] gfx908 scheduling
2019-07-11 21:25:00 +00:00
SIShrinkInstructions.cpp
AMDGPU: Don't fold S_NOPs with implicit operands
2019-10-30 14:40:56 -07:00
SIWholeQuadMode.cpp
Sink all InitializePasses.h includes
2019-11-13 16:34:37 -08:00
SMInstructions.td
[AMDGPU] deduplicate tablegen predicates
2019-11-04 12:19:17 -08:00
SOPInstructions.td
AMDGPU: Only allow regs for s_movrel_{b32|b64}
2020-01-03 15:25:49 -05:00
VIInstrFormats.td
…
VIInstructions.td
…
VOP1Instructions.td
[AMDGPU][MC][GFX10] Enabled v_movrel*[sdwa|dpp|dpp8] opcodes
2019-11-18 17:23:40 +03:00
VOP2Instructions.td
AMDGPU/GlobalISel: Select mul24 intrinsics
2019-12-30 14:24:25 -05:00
VOP3Instructions.td
[AMDGPU] deduplicate tablegen predicates
2019-11-04 12:19:17 -08:00
VOP3PInstructions.td
[AMDGPU] deduplicate tablegen predicates
2019-11-04 12:19:17 -08:00
VOPCInstructions.td
[AMDGPU] deduplicate tablegen predicates
2019-11-04 12:19:17 -08:00
VOPInstructions.td
[AMDGPU] copy OtherPredicates from pseudo to VOP3_Real
2019-09-26 21:06:17 +00:00