yanming 8d9d8f866a [RISCV] Define risc-v's own register class to model FP Register. ...

The default RegisterClass is not enough to model RISCV Register.
We define risc-v's own register class to model FP Register.
This helps to better estimate the register pressure in the loop-vectorize.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D126854

2022-06-06 14:43:52 +08:00

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lit.local.cfg

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low-trip-count.ll

[LoopVectorize] Permit tail-folding for low trip counts using scalable vectors

2022-05-16 09:14:24 +01:00

masked_gather_scatter.ll

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reg-usage.ll

[RISCV] Define risc-v's own register class to model FP Register.

2022-06-06 14:43:52 +08:00

riscv-interleaved.ll

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riscv-unroll.ll

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riscv-vector-reverse.ll

[RISCV] Add test for experimental.vector.reverse

2022-05-27 06:30:07 +00:00

scalable-reductions.ll

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scalable-vf-hint.ll

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unroll-in-loop-vectorizer.ll

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