3e35ba53e2
Insert waitcnts for loads and atomics before stores with system scope. Scope is field in instruction encoding and corresponds to desired coherence level in cache hierarchy. Intrinsic stores can set scope in cache policy operand. If volatile keyword is used on generic stores memory legalizer will set scope to system. Generic stores, by default, get lowest scope level. Waitcnts are not required if it is guaranteed that memory is cached. For example vulkan shaders can guarantee this. TODO: implement flag for frontends to give us a hint not to insert waits. Expecting vulkan flag to be implemented as vulkan:private MMRA.
27 lines
1.2 KiB
LLVM
27 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX12 %s
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; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX12 %s
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define amdgpu_ps void @intrinsic_store_system_scope(i32 %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
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; GFX12-LABEL: intrinsic_store_system_scope:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: buffer_store_b32 v0, v[1:2], s[0:3], s4 idxen offen scope:SCOPE_SYS
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; GFX12-NEXT: s_nop 0
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; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX12-NEXT: s_endpgm
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call void @llvm.amdgcn.struct.buffer.store.i32(i32 %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 24)
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ret void
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}
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define amdgpu_ps void @generic_store_volatile(i32 %val, ptr addrspace(1) %out) {
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; GFX12-LABEL: generic_store_volatile:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: global_store_b32 v[1:2], v0, off scope:SCOPE_SYS
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; GFX12-NEXT: s_wait_storecnt 0x0
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; GFX12-NEXT: s_nop 0
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; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX12-NEXT: s_endpgm
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store volatile i32 %val, ptr addrspace(1) %out
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ret void
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}
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