9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
98 lines
3.6 KiB
LLVM
98 lines
3.6 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
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; GCN-LABEL: {{^}}trunc_i64_bitcast_v2i32:
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; GCN: buffer_load_dword v
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; GCN: buffer_store_dword v
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define amdgpu_kernel void @trunc_i64_bitcast_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%ld = load <2 x i32>, ptr addrspace(1) %in
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%bc = bitcast <2 x i32> %ld to i64
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%trunc = trunc i64 %bc to i32
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store i32 %trunc, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}trunc_i96_bitcast_v3i32:
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; GCN: buffer_load_dword v
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; GCN: buffer_store_dword v
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define amdgpu_kernel void @trunc_i96_bitcast_v3i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%ld = load <3 x i32>, ptr addrspace(1) %in
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%bc = bitcast <3 x i32> %ld to i96
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%trunc = trunc i96 %bc to i32
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store i32 %trunc, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}trunc_i128_bitcast_v4i32:
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; GCN: buffer_load_dword v
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; GCN: buffer_store_dword v
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define amdgpu_kernel void @trunc_i128_bitcast_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%ld = load <4 x i32>, ptr addrspace(1) %in
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%bc = bitcast <4 x i32> %ld to i128
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%trunc = trunc i128 %bc to i32
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store i32 %trunc, ptr addrspace(1) %out
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ret void
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}
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; Don't want load width reduced in this case.
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; GCN-LABEL: {{^}}trunc_i16_bitcast_v2i16:
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; GCN: buffer_load_dword [[VAL:v[0-9]+]]
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; GCN: buffer_store_short [[VAL]]
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define amdgpu_kernel void @trunc_i16_bitcast_v2i16(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%ld = load <2 x i16>, ptr addrspace(1) %in
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%bc = bitcast <2 x i16> %ld to i32
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%trunc = trunc i32 %bc to i16
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store i16 %trunc, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}trunc_i16_bitcast_v4i16:
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; FIXME We need to teach the dagcombiner to reduce load width for:
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; t21: v2i32,ch = load<LD8[%in(addrspace=1)]> t12, t10, undef:i64
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; t23: i64 = bitcast t21
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; t30: i16 = truncate t23
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; GCN: buffer_load_dword v[[VAL:[0-9]+]]
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; GCN: buffer_store_short v[[VAL]], off
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define amdgpu_kernel void @trunc_i16_bitcast_v4i16(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%ld = load <4 x i16>, ptr addrspace(1) %in
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%bc = bitcast <4 x i16> %ld to i64
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%trunc = trunc i64 %bc to i16
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store i16 %trunc, ptr addrspace(1) %out
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ret void
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}
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; FIXME: Consistently shrink or not here
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; GCN-LABEL: {{^}}trunc_i8_bitcast_v2i8:
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; SI: buffer_load_ubyte [[VAL:v[0-9]+]]
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; VI: buffer_load_ushort [[VAL:v[0-9]+]]
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; GCN: buffer_store_byte [[VAL]]
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define amdgpu_kernel void @trunc_i8_bitcast_v2i8(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%ld = load <2 x i8>, ptr addrspace(1) %in
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%bc = bitcast <2 x i8> %ld to i16
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%trunc = trunc i16 %bc to i8
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store i8 %trunc, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}trunc_i32_bitcast_v4i8:
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; GCN: buffer_load_dword [[VAL:v[0-9]+]]
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; GCN: buffer_store_byte [[VAL]]
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define amdgpu_kernel void @trunc_i32_bitcast_v4i8(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%ld = load <4 x i8>, ptr addrspace(1) %in
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%bc = bitcast <4 x i8> %ld to i32
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%trunc = trunc i32 %bc to i8
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store i8 %trunc, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: {{^}}trunc_i24_bitcast_v3i8:
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; GCN: buffer_load_dword [[VAL:v[0-9]+]]
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; GCN: buffer_store_byte [[VAL]]
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define amdgpu_kernel void @trunc_i24_bitcast_v3i8(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%ld = load <3 x i8>, ptr addrspace(1) %in
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%bc = bitcast <3 x i8> %ld to i24
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%trunc = trunc i24 %bc to i8
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store i8 %trunc, ptr addrspace(1) %out
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ret void
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}
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