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clang-p2996/llvm/lib/Target/AArch64
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Paul Walker f78e6a3095 [SVE] Code generation for fixed length vector truncates. 
Lower fixed length vector truncates to a sequence of SVE UZP1 instructions.

Differential Revision: https://reviews.llvm.org/D83395
2020-07-10 10:37:19 +00:00
..
AsmParser
[AArch64][AsmParser] Fix debug output in a few instructions
2020-06-09 09:02:59 +00:00
Disassembler
[AArch64] Emit warning when disassembling unpredictable LDRAA and LDRAB
2020-06-25 15:56:36 +01:00
GISel
[SVE][CodeGen] Fix bug when falling back to DAG ISel
2020-07-07 09:23:04 +01:00
MCTargetDesc
[AArch64] Print the immediate operand for SPACE pseudo instruction
2020-06-15 20:55:53 -07:00
TargetInfo
CMake: Make most target symbols hidden by default
2020-01-14 19:46:52 -08:00
Utils
[AArch64][SVE] Add patterns for unpredicated load/store to frame-indices.
2020-01-22 14:32:27 +00:00
AArch64.h
[AArch64] Extend AArch64SLSHardeningPass to harden BLR instructions.
2020-06-12 07:34:33 +01:00
AArch64.td
[ARM] Add Cortex-A77 Support for Clang and LLVM
2020-07-03 13:00:54 +01:00
AArch64A53Fix835769.cpp
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AArch64A57FPLoadBalancing.cpp
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AArch64AdvSIMDScalarPass.cpp
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AArch64AsmPrinter.cpp
[DebugInfo] Update MachineInstr to help support variadic DBG_VALUE instructions
2020-06-22 16:01:12 +01:00
AArch64BranchTargets.cpp
[AArch64] Fix BTI instruction emission.
2020-06-15 15:04:36 +02:00
AArch64CallingConvention.cpp
[Alignment][NFC] Use Align for TargetCallingConv::OrigAlign
2020-06-25 13:21:22 +00:00
AArch64CallingConvention.h
…
AArch64CallingConvention.td
[Alignment][NFC] Use Align for TargetCallingConv::OrigAlign
2020-06-25 13:21:22 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp
[CallSiteInfo] Handle bundles when updating call site info
2020-02-27 13:57:06 +01:00
AArch64CollectLOH.cpp
[AArch64] Fix CollectLOH creating an AdrpAdd LOH when there's a live used reg
2020-06-01 16:00:55 -07:00
AArch64Combine.td
[gicombiner] Allow generated combiners to store additional members
2020-06-16 14:47:04 -07:00
AArch64CompressJumpTables.cpp
[Alignment][NFC] Deprecate Align::None()
2020-01-24 12:53:58 +01:00
AArch64CondBrTuning.cpp
[AArch64CondBrTuning] Ignore debug insts when scanning for NZCV clobbers [10/14]
2020-04-22 17:03:40 -07:00
AArch64ConditionalCompares.cpp
DomTree: Remove getChildren() accessor
2020-07-06 21:58:11 +02:00
AArch64ConditionOptimizer.cpp
MachineBasicBlock::updateTerminator now requires an explicit layout successor.
2020-06-06 22:30:51 -04:00
AArch64DeadRegisterDefinitionsPass.cpp
…
AArch64ExpandImm.cpp
…
AArch64ExpandImm.h
…
AArch64ExpandPseudoInsts.cpp
[SVE] Fix invalid assert in expand_DestructiveOp.
2020-07-04 09:21:40 +00:00
AArch64FalkorHWPFFix.cpp
[TargetRegisterInfo] Default trackLivenessAfterRegAlloc() to true
2020-01-19 14:20:37 -08:00
AArch64FastISel.cpp
Silence GCC 7 warning
2020-06-16 11:42:52 +01:00
AArch64FrameLowering.cpp
[NFC][AArch64] Refactor getArgumentPopSize
2020-07-09 11:58:15 -07:00
AArch64FrameLowering.h
CodeGen: Use Register in TargetFrameLowering
2020-04-07 17:07:44 -04:00
AArch64GenRegisterBankInfo.def
…
AArch64InstrAtomics.td
…
AArch64InstrFormats.td
[AArch64] Emit warning when disassembling unpredictable LDRAA and LDRAB
2020-06-25 15:56:36 +01:00
AArch64InstrGISel.td
[AArch64][GlobalISel] Add G_EXT and select ext using it
2020-06-15 12:20:59 -07:00
AArch64InstrInfo.cpp
[Target] As part of using inclusive language within the llvm project,
2020-06-20 00:06:39 -07:00
AArch64InstrInfo.h
[AArch64][SVE] NFC: Rename isOrig -> isReverseInstr
2020-07-02 17:01:15 +01:00
AArch64InstrInfo.td
[ARM] Generate [SU]RHADD from (b - (~a)) >> 1
2020-07-03 16:00:06 +01:00
AArch64ISelDAGToDAG.cpp
[SVE] Custom ISel for fixed length extract/insert_subvector.
2020-07-08 09:49:28 +00:00
AArch64ISelLowering.cpp
[SVE] Code generation for fixed length vector truncates.
2020-07-10 10:37:19 +00:00
AArch64ISelLowering.h
[SVE] Code generation for fixed length vector truncates.
2020-07-10 10:37:19 +00:00
AArch64LoadStoreOptimizer.cpp
[AArch64] Fix ldst-opt of multiple disjunct subregs.
2020-06-08 20:18:24 +01:00
AArch64MachineFunctionInfo.cpp
MachineFunctionInfo for AArch64 in MIR
2020-04-17 15:16:59 -07:00
AArch64MachineFunctionInfo.h
[MachineOutliner] Annotation for outlined functions in AArch64
2020-04-20 13:33:31 -07:00
AArch64MacroFusion.cpp
…
AArch64MacroFusion.h
…
AArch64MCInstLower.cpp
…
AArch64MCInstLower.h
…
AArch64PBQPRegAlloc.cpp
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AArch64PBQPRegAlloc.h
…
AArch64PerfectShuffle.h
…
AArch64PfmCounters.td
…
AArch64PromoteConstant.cpp
[AArch64] Don't promote constants with float ConstantExpr.
2020-05-13 23:31:47 +01:00
AArch64RedundantCopyElimination.cpp
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AArch64RegisterBanks.td
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AArch64RegisterInfo.cpp
[AArch64] Treat x18 as callee-saved in functions with windows calling convention on non-windows OSes
2020-05-30 09:22:09 +03:00
AArch64RegisterInfo.h
[AArch64] Provide Darwin variants of most calling conventions
2020-05-20 16:03:48 -07:00
AArch64RegisterInfo.td
[AArch64][BFloat] basic AArch64 bfloat support
2020-05-27 15:26:40 +01:00
AArch64SchedA53.td
[AARch64] Add Marvell ThunderX3T110 support
2020-05-13 16:58:51 -07:00
AArch64SchedA57.td
[AARch64] Add Marvell ThunderX3T110 support
2020-05-13 16:58:51 -07:00
AArch64SchedA57WriteRes.td
…
AArch64SchedCyclone.td
[AARch64] Add Marvell ThunderX3T110 support
2020-05-13 16:58:51 -07:00
AArch64SchedExynosM3.td
[AARch64] Add Marvell ThunderX3T110 support
2020-05-13 16:58:51 -07:00
AArch64SchedExynosM4.td
[AARch64] Add Marvell ThunderX3T110 support
2020-05-13 16:58:51 -07:00
AArch64SchedExynosM5.td
[AARch64] Add Marvell ThunderX3T110 support
2020-05-13 16:58:51 -07:00
AArch64SchedFalkor.td
[AARch64] Add Marvell ThunderX3T110 support
2020-05-13 16:58:51 -07:00
AArch64SchedFalkorDetails.td
[AArch64] Add BIT/BIF support.
2020-02-14 14:19:39 +00:00
AArch64SchedKryo.td
[AARch64] Add Marvell ThunderX3T110 support
2020-05-13 16:58:51 -07:00
AArch64SchedKryoDetails.td
[AArch64] Add BIT/BIF support.
2020-02-14 14:19:39 +00:00
AArch64SchedPredExynos.td
…
AArch64SchedPredicates.td
…
AArch64SchedThunderX2T99.td
[AARch64] Add Marvell ThunderX3T110 support
2020-05-13 16:58:51 -07:00
AArch64SchedThunderX3T110.td
[AARch64] Add Marvell ThunderX3T110 support
2020-05-13 16:58:51 -07:00
AArch64SchedThunderX.td
[AARch64] Add Marvell ThunderX3T110 support
2020-05-13 16:58:51 -07:00
AArch64Schedule.td
…
AArch64SelectionDAGInfo.cpp
[Alignment][NFC] Migrate SelectionDAGTargetInfo::EmitTargetCodeForMemset to Align
2020-06-30 12:46:26 +00:00
AArch64SelectionDAGInfo.h
[Alignment][NFC] Migrate SelectionDAGTargetInfo::EmitTargetCodeForMemset to Align
2020-06-30 12:46:26 +00:00
AArch64SIMDInstrOpt.cpp
Make llvm::StringRef to std::string conversions explicit.
2020-01-28 23:25:25 +01:00
AArch64SLSHardening.cpp
[NFC] Clean up uses of MachineModuleInfoWrapperPass
2020-07-01 09:45:05 -07:00
AArch64SpeculationHardening.cpp
…
AArch64StackOffset.h
Explicitly include <cassert> when using assert
2020-03-02 22:45:28 +01:00
AArch64StackTagging.cpp
[SVE] Remove calls to VectorType::getNumElements from AArch64
2020-06-30 11:17:50 -07:00
AArch64StackTaggingPreRA.cpp
…
AArch64StorePairSuppress.cpp
Add OffsetIsScalable to getMemOperandWithOffset
2020-02-18 15:53:29 +00:00
AArch64Subtarget.cpp
[ARM] Add Cortex-A77 Support for Clang and LLVM
2020-07-03 13:00:54 +01:00
AArch64Subtarget.h
[ARM] Add Cortex-A77 Support for Clang and LLVM
2020-07-03 13:00:54 +01:00
AArch64SVEInstrInfo.td
[AArch64][SVE] Add lowering for llvm.fma.
2020-07-09 16:12:41 -07:00
AArch64SystemOperands.td
[AArch64] Remove inexistent system register ERXTS_EL1
2020-04-29 16:43:48 +01:00
AArch64TargetMachine.cpp
[AArch64] Extend AArch64SLSHardeningPass to harden BLR instructions.
2020-06-12 07:34:33 +01:00
AArch64TargetMachine.h
MachineFunctionInfo for AArch64 in MIR
2020-04-17 15:16:59 -07:00
AArch64TargetObjectFile.cpp
[X86] Reland D71360 Clean up UseInitArray initialization for X86ELFTargetObjectFile
2020-03-20 21:57:34 -07:00
AArch64TargetObjectFile.h
[llvm][ELF][AArch64] Handle R_AARCH64_PLT32 relocation
2020-06-10 11:34:16 -07:00
AArch64TargetTransformInfo.cpp
Revert "[NFC] Separate Peeling Properties into its own struct"
2020-07-08 21:43:32 +02:00
AArch64TargetTransformInfo.h
[SVE] Scalarize fixed length masked loads and stores.
2020-07-09 10:47:04 +00:00
CMakeLists.txt
[AArch64] Introduce AArch64SLSHardeningPass, implementing hardening of RET and BR instructions.
2020-06-11 07:51:17 +01:00
LLVMBuild.txt
…
SVEInstrFormats.td
[AArch64][SVE] NFC: Rename isOrig -> isReverseInstr
2020-07-02 17:01:15 +01:00
SVEIntrinsicOpts.cpp
[SVEIntrinsicOpts] NFC: Remove unused isReinterpretFromBool for no-assert builds
2020-04-21 09:49:22 +01:00