caio/clang-p2996
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
ec00c9cdeb5ee9fc7846cb3d2a4d53eba2c35a43
clang-p2996/llvm/lib/Target/RISCV
History
Craig Topper f943c58cae [RISCC] Add missing words to comment. NFC
2022-02-01 07:39:51 -08:00
..
AsmParser
[RISCV][NFC] Make Zb* instruction naming match the convention used elsewhere in the RISC-V backend
2022-01-28 15:20:37 +00:00
Disassembler
Move TargetRegistry.(h|cpp) from Support to MC
2021-10-08 14:51:48 -07:00
MCTargetDesc
[RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes.
2022-01-28 09:51:49 -08:00
TargetInfo
Fix shlib builds for all lib/Target/*/TargetInfo libs
2021-10-08 15:21:13 -07:00
CMakeLists.txt
[RISCV] Add an MIR pass to replace redundant sext.w instructions with copies.
2022-01-06 08:23:42 -08:00
RISCV.h
[RISCV] Add an MIR pass to replace redundant sext.w instructions with copies.
2022-01-06 08:23:42 -08:00
RISCV.td
[RISCV] Separate the Zfhmin and Zfh extensions.
2022-01-31 09:06:43 -08:00
RISCVAsmPrinter.cpp
Move TargetRegistry.(h|cpp) from Support to MC
2021-10-08 14:51:48 -07:00
RISCVCallingConv.td
…
RISCVCallLowering.cpp
…
RISCVCallLowering.h
…
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes.
2022-01-28 09:51:49 -08:00
RISCVExpandPseudoInsts.cpp
[RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes.
2022-01-28 09:51:49 -08:00
RISCVFrameLowering.cpp
[RISCV] Fix the bug in the register allocator caused by reserved BP.
2022-01-21 01:23:01 +00:00
RISCVFrameLowering.h
[RISCV] Enable shrink wrap by default
2021-09-02 09:47:58 -05:00
RISCVGatherScatterLowering.cpp
[RISCV] Teach RISCVGatherScatterLowering to handle more complex recurrence start values.
2022-01-04 10:13:34 -08:00
RISCVInsertVSETVLI.cpp
[RISCC] Add missing words to comment. NFC
2022-02-01 07:39:51 -08:00
RISCVInstrFormats.td
[RISCV] Add strictfp support for compares.
2022-01-11 20:01:41 -08:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
[RISCV] Remove Zvamo Extention
2021-12-20 10:28:39 +08:00
RISCVInstrInfo.cpp
[RISCV] Use tablegen size for getInstSizeInBytes.
2022-01-28 09:21:28 -08:00
RISCVInstrInfo.h
[RISCV] Use AdjustInstrPostInstrSelection to insert a FRM dependency for scalar FP instructions with dynamic rounding mode.
2021-12-14 10:17:57 -08:00
RISCVInstrInfo.td
[RISCV] Use tablegen size for getInstSizeInBytes.
2022-01-28 09:21:28 -08:00
RISCVInstrInfoA.td
[RISCV] Use tablegen size for getInstSizeInBytes.
2022-01-28 09:21:28 -08:00
RISCVInstrInfoC.td
[llvm-tblgen][RISCV] Make llvm-tblgen RISCVCompressInstEmitter to be common infra across different targets
2021-11-18 11:14:27 +08:00
RISCVInstrInfoD.td
[RISCV] Optimize lowering of floating-point -0.0
2022-01-20 11:46:28 +00:00
RISCVInstrInfoF.td
[RISCV] Optimize lowering of floating-point -0.0
2022-01-20 11:46:28 +00:00
RISCVInstrInfoM.td
[RISCV] Use MULHU for more division by constant cases.
2021-12-09 09:10:14 -08:00
RISCVInstrInfoV.td
[RISCV] Remove Zvlsseg extension.
2022-01-20 12:40:07 -08:00
RISCVInstrInfoVPseudos.td
[RISCV] Use tablegen size for getInstSizeInBytes.
2022-01-28 09:21:28 -08:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Prefer vmslt.vx v0, v8, zero over vmsle.vi v0, v8, -1.
2022-01-27 11:48:27 -08:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Add support for matching vwmulsu from fixed vectors
2022-01-28 02:33:30 +00:00
RISCVInstrInfoZb.td
[RISCV] Lower riscv_zip/unzip intrinsic to RISCVISD::SHFL/UNSHFL.
2022-01-30 13:27:41 -08:00
RISCVInstrInfoZfh.td
[RISCV] Separate the Zfhmin and Zfh extensions.
2022-01-31 09:06:43 -08:00
RISCVInstrInfoZk.td
[RISCV] Adjust some comments.
2022-02-01 22:53:54 +08:00
RISCVInstructionSelector.cpp
[Target] Remove redundant member initialization (NFC)
2022-01-06 22:01:44 -08:00
RISCVISelDAGToDAG.cpp
[RISCV][NFC] Make Zb* instruction naming match the convention used elsewhere in the RISC-V backend
2022-01-28 15:20:37 +00:00
RISCVISelDAGToDAG.h
[RISCV] Add the passthru operand for RVV nomask load intrinsics.
2022-01-25 17:31:36 -08:00
RISCVISelLowering.cpp
[RISCV] Add a fatal error if ISD::VSCALE is used with Zvl32b.
2022-01-31 09:13:14 -08:00
RISCVISelLowering.h
[RISCV] Remove RISCVISD::BREV8 and use RISCVISD::GREV instead.
2022-01-29 22:45:43 -08:00
RISCVLegalizerInfo.cpp
…
RISCVLegalizerInfo.h
…
RISCVMachineFunctionInfo.h
…
RISCVMCInstLower.cpp
[NFC] Use Register instead of unsigned
2022-01-19 20:17:04 +08:00
RISCVMergeBaseOffset.cpp
[RISCV] Remove unused member variable. NFC
2021-10-14 12:56:47 -07:00
RISCVRegisterBankInfo.cpp
Revert "[llvm] Remove redundant member initialization (NFC)"
2022-01-03 11:28:47 -08:00
RISCVRegisterBankInfo.h
…
RISCVRegisterBanks.td
…
RISCVRegisterInfo.cpp
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
RISCVRegisterInfo.h
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
RISCVRegisterInfo.td
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
RISCVSchedRocket.td
[RISCV] add support for zbkx subextension in MC layer.
2022-01-24 20:38:46 +08:00
RISCVSchedSiFive7.td
[RISCV] add support for zbkx subextension in MC layer.
2022-01-24 20:38:46 +08:00
RISCVSchedule.td
…
RISCVScheduleB.td
[RISCV] Add instruction schedule for Zbc extension and Zbs extension
2022-01-18 07:31:50 +00:00
RISCVScheduleV.td
…
RISCVSExtWRemoval.cpp
[RISCV][NFC] Make Zb* instruction naming match the convention used elsewhere in the RISC-V backend
2022-01-28 15:20:37 +00:00
RISCVSubtarget.cpp
[RISCV] Fix support of vlen = 64.
2022-01-26 16:31:21 +08:00
RISCVSubtarget.h
[RISCV] Update the computeKnownBitsForTargetNode for RISCVISD::READ_VLENB to consider Zve/Zvl.
2022-01-31 09:13:14 -08:00
RISCVSystemOperands.td
[RISCV] Initially support the K-extension instructions on the LLVM MC layer
2022-01-24 14:45:35 +08:00
RISCVTargetMachine.cpp
[RISCV] Add an MIR pass to replace redundant sext.w instructions with copies.
2022-01-06 08:23:42 -08:00
RISCVTargetMachine.h
…
RISCVTargetObjectFile.cpp
…
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[RISCV] Add initial support for getRegUsageForType and getNumberOfRegisters
2022-01-17 15:27:54 +08:00
RISCVTargetTransformInfo.h
[RISCV] Add initial support for getRegUsageForType and getNumberOfRegisters
2022-01-17 15:27:54 +08:00